M25P20 Просмотр технического описания (PDF) - STMicroelectronics

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M25P20

2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface

STMicroelectronics 

M25P20

Revision history

Table 24. Document revision history (continued)

Date

Revision

Changes

01-Dec-2005

22-Dec-2005

50MHz operation added (see Table 20: AC Characteristics (50MHz

Operation, Device Grade 6)). All packages are ECOPACK®. Blank option

removed from under Plating Technology in Table 23: Ordering Information

7.0

Scheme. MLP package renamed as VFQFPN, silhouette and package

mechanical drawing updated (see package silhouette on page 1 and

Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat

Package No lead, 6x5mm, Package Outline. Note added to <Blue>Figure

26. and Figure 27 Read Identification (RDID) instruction added.

8.0

tRES1 and tRES2 modified in Table 20: AC Characteristics (50MHz

Operation, Device Grade 6). Titles of Figure 27 and Table 22 corrected.

14-Apr-2006

05-Jun-2006

The data contained in Table 11, Table 16 and Table 18 is no longer

preliminary data.

Figure 3: Bus Master and memory devices on the SPI Bus modified and

Note 2 added.

40MHz frequency condition modified for ICC3 in Table 14: DC

Characteristics (Device Grade 3).

9 Table 16: Instruction Times (Device Grade 3) shows preliminary data.

Device Grade distinction removed, Condition changed for the Data

Retention parameter in Table 11: Data Retention and Endurance.

VWI parameter for Device Grade 3 added to Table 8: Power-Up Timing

and VWI Threshold.

SO8 package specifications updated (see Figure 26 and Table 21).

/X Process added to Table 23: Ordering Information Scheme.

tRES1 and tRES2 parameter timings changed for devices produced with the

“X” process technology in Table 18 and Table 19.

10

SO8 Narrow package specifications updated (see Figure 26 and

Table 21).

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