LXT300Z Просмотр технического описания (PDF) - Level One

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LXT300Z

Advanced T1/E1 Short-Haul Transceivers

Level One 

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'2 5HFHLYH 1HJDWLYH 'DWDâ 5HFHLYH 3RVLWLYH 'DWDï Received data outputs. A signal on

RNEG corresponds to receipt of a negative pulse on RTIP and RRING. A signal on

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'2 RPOS corresponds to receipt of a positive pulse on RTIP and RRING. RNEG and

RPOS outputs are Non-Return-to-Zero (NRZ). Both outputs are stable and valid on the

rising edge of RCLK.

LXT300Z only: In the Host Mode, CLKE determines the clock edge at which these out-

puts are stable and valid. In the Hardware Mode both outputs are stable and valid on

the rising edge of RCLK.

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'2 5HFRYHUHG &ORFNï This is the clock recovered from the signal received at RTIP and

RRING.

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;7$/,1 $, &U\VWDO ,QSXWâ &U\VWDO 2XWSXW õ/;7êíí=ôï An external crystal operating at four

times the bit rate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an 18.7

ìí ;7$/287 $2 pF load) is required to enable the jitter attenuation function of the LXT300Z. These

pins may also be used to disable the jitter attenuator by connecting the XTALIN pin to

the positive supply through a resistor, and floating the XTALOUT pin.

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'2 'ULYHU 3HUIRUPDQFH 0RQLWRUï DPM goes High when the transmit monitor loop

(MTIP and MRING) does not detect a signal for 63 ±2 clock periods. DPM remains

High until a signal is detected.

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'2 /RVV RI 6LJQDOï LOS goes High when 175 consecutive spaces have been detected.

LOS returns Low when a mark is detected.

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$2 7UDQVPLW 7LSâ 7UDQVPLW 5LQJï Differential Driver Outputs. These outputs are

designed to drive a 25 Ω load. The transmitter will drive 100 Ω shielded twisted-pair

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75,1* $2 cable through a 1:2 step-up transformer without additional components. To drive

75 Ω coaxial cable, two 2.2 Ω resistors are required in series with the transformer.

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$, 5HFHLYH 7LSâ 5HFHLYH 5LQJï The AMI signal received from the line is applied at these

pins. A center-tapped, center-grounded, 2:1 step-up transformer is required on these

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$, pins. Data and clock from the signal applied at these pins are recovered and output on

the RPOS/RNEG and RCLK pins.

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