LXT300Z Просмотр технического описания (PDF) - Level One
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LXT300Z Datasheet PDF : 20 Pages
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Figure 5 is a typical 1.544 Mbps T1 application. The
LXT300Z is shown in the Host Mode with a typical T1/
ESF framer providing the digital interface with the host
controller. Both devices are controlled through the serial
interface. An LXP600A Clock Adapter (CLAD) provides
the 2.048 MHz system backplane clock, locked to the
recovered 1.544 MHz clock signal. The power supply
inputs are tied to a common bus with appropriate decou-
pling capacitors installed (68 µF on the transmit side, 1.0
µF and 0.1 µF on the receive side).
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