LXT972M Просмотр технического описания (PDF) - Intel

Номер в каталоге

Компоненты Описание

производитель

LXT972M

Single-Port 10/100 Mbps PHY Transceiver

Intel 

Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver

2.0

Block Diagram for Intel® LXT972M Transceiver

Figure 1 is a block diagram of the LXT972M Transceiver. (This block diagram is the same as the

block diagram on the first page of this document. This copy of the block diagram appears here as a

convenience to the reader.)

Figure 1. Intel® LXT972M Transceiver Block Diagram

RESET_L

ADDR[1:0]

MDIO

MDC

TX_EN

TXD[3:0]

TX_CLK

LED/CFG[3:1]

COL

RX_CLK

RXD[3:0]

RX_DV

CRS

RX_ER

Management /

Mode Select

Logic

Register Set

Clock

Generator

Power Supply

Parallel/Serial

Converter

Manchester

Encoder

10

Scrambler 100

& Encoder

Register

Set

Auto

Negotiation

OSP

Pulse

Shaper

+

TP

Driver -

TP Out

JTAG

Collision

Detect

Clock

Generator

Serial-to-

Parallel

Carrier Sense Converter

Data Valid

Error Detect

Manchester

10 Decoder

100

Decoder &

Descrambler

Media

Select

OSP

Slicer

OSP

Adaptive EQ with

Baseline Wander

Cancellation

+

100TX

-

+

10BT

-

TP In

VCC

GND

REFCLK/XI

XO

TPOP

TPON

TDI

5 TDO

TMS

TCK

TRST_L

TPIP

TPIN

B3387-13

Datasheet

11

Document Number: 302875-005

Revision Date: 27-Oct-2005

Share Link: