LV4912GP Просмотр технического описания (PDF) - SANYO -> Panasonic
Номер в каталоге
Компоненты Описание
производитель
LV4912GP Datasheet PDF : 11 Pages
| |||
LV4912GP
(2) Power Down sequence
The OFF Time should secure more than 100msec for reduction of the popping noise.
STBY
Internal power
supply
MUTE
MUTECAP
Output pin
OFF Time
Capacitors for Power supply and pin arrangement
1. Capacitors for power supply
The capacitors C2 and C3 for power supply connected between IC pins must be inserted using the shortest lines
possible.
17 PWR_VD
C2
1μF
22 PWR_GND
2 PRE_VD
C3
1μF
3 PRE_GND
2. Pin arrangement of the test pins (pins 15 and 16)
The test pins (pins 15 and 16) are used as pins for testing before shipment. These pins are not used normally. Therefore,
these pins must be left open if the pin arrangement is not performed. Please make sure to connect these pins to GNDs if
the pin arrangement is performed.
No.A1173-8/11
Share Link: 