LTC6801IG(V2) Просмотр технического описания (PDF) - Linear Technology
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LTC6801IG Datasheet PDF : 28 Pages
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LTC6801
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
DC Specifications
VERR
VCELL
VCM
Measurement Error
Cell Voltage Range
Common Mode Voltage Range Measured
Relative to V–
VCELL
VCELL
VCELL
VCELL
>
>
≤
≤
0.8V,
0.8V,
0.8V,
0.8V,
10V
10V
10V
10V
<
<
<
<
V+
V+
V+
V+
<
<
<
<
50V
50V
50V
50V
Full Scale Voltage Range
VERR Specifications Met
Range of Inputs Cn, n = 3 to 11
Range of Input C2
Range of Input C1
–0.5
l –1
–1.5
l –2
0.5
%
1
%
1.5
%
2
%
5
V
l 1.8
l 1.2
l
0
5•n
V
10
V
5
V
VOV
Overvoltage (OV) Detection Level
Programmed for
10V < V+ < 50V
4.128V,
Increasing
VCELL,
l
4.079
4.120
4.161
V
VUV
Undervoltage (UV) Detection Level
Programmed for
10V < V+ < 50V
2.112V,
Decreasing
VCELL,
l
2.087
2.108
2.129
V
VTV
Temperature Input Detection Level Error 10V < V+ < 50V
(Relative to VREF/2)
HYS
UV/OV Detection Hysteresis Error
10V < V+ < 50V
(Relative to Selected Value)
l –18
l –25
12
mV
25
%
VREF
Reference Pin Voltage
VREF Pin Loaded With 100k to V–
3.043 3.058 3.073
V
l 3.038 3.058 3.078
V
Reference Voltage Temperature Coefficient
5
ppm/˚C
Reference Voltage Hysteresis
Reference Voltage Long Term Drift
50
ppm
60
ppm/√khr
VREG
Regulator Pin Voltage
10 < VS < 50, No Load
10 < VS < 50, ILOAD = 4mA
l 4.5
5
5.5
V
l 4.1
4.8
V
Regulator Pin Short Circuit Current Limit
l
5
9
mA
VS
Supply Voltage, V+ Relative to V–
VERR Specifications Met
l 10
50
V
IB
Input Bias Current
In/Out of Pins C1 Thru C12
When Measuring Cells During Self Test
100
μA
When Measuring Cells
l –10
10
μA
When Idle
1
nA
IM
Supply Current, Monitor Mode
Current Into the V+ Pin While Monitoring
for UV and OV Conditions, FENA = 10kHz
Continuous Monitoring
l 500
700 1000
μA
Monitor Every 130ms
200
μA
Monitor Every 500ms
90
μA
IQS
Supply Current, Idle
LTC6801 Timing Specifications
Current into the V+ Pin When Idle, FENA = 0 l 20
30
40
μA
TCYCLE
Measurement Cycle Time
DC = CC1 = CC0 = VREG
FENA
Valid EIN/EIN Frequency
TENA
Valid EIN/EIN Period = 1/ FENA
DCENA
Valid EIN/EIN Duty Cycle
FENA = 50kHz
LTC6801 Single Ended Digital I/O Specifications (SLT, SLTOK Pins)
VIH
Digital Input Voltage High
SLT Pin
VIL
Digital Input Voltage Low
SLT Pin
VODL
Digital Output Voltage Low, Open Drain
SLT Pin, 10k to VREG
VOH
Digital Output Voltage High
SLTOK Pin, 10k to V–
VOL
Digital Output Voltage Low
SLTOK Pin, 10k to VREG
l 13.5 15.5 17.5
ms
l
2
50
kHz
l 20
500
μs
l 40
60
%
l
2
l
l
l VREG – 0.3
l
V
0.5
V
0.3
V
V
0.3
V
6801p
3
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