LTC3548-2 Просмотр технического описания (PDF) - Linear Technology
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LTC3548-2
Linear Technology
LTC3548-2 Datasheet PDF : 16 Pages
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LTC3548-2
APPLICATIONS INFORMATION
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and the
output capacitor size. Typically, 3 to 4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, VDROOP, is usually
about 2 to 3 times the linear drop of the first cycle. Thus,
a good place to start is with the output capacitor size of
approximately:
COUT
≈
2.5
fO
ΔIOUT
• VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage for Channel 2
The LTC3548-2 develops a 0.6V reference voltage be-
tween the feedback pin, VFB2, and the ground as shown
in Figure 2. The output voltage, VOUT2, is set by a resistive
divider according to the following formula:
VOUT2
=
0.6V
⎛
⎝⎜
1+
R2 ⎞
R1⎠⎟
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feed forward capaci-
tor CF may also be used. Great care should be taken to
route the VOUT1, VFB2 line away from noise sources, such
as the inductor or the SW line.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are above –8.5% of regulation, a timer is started
which releases POR after 218 clock cycles (about 117ms
in pulse-skipping mode). This delay can be significantly
longer in Burst Mode operation with low load currents,
since the clock cycles only occur during a burst and there
could be milliseconds of time between bursts. This can
be bypassed by tying the POR output to the MODE/SYNC
input, to force pulse-skipping mode during a reset. In ad-
dition, if the output voltage faults during Burst Mode sleep,
POR could have a slight delay for an undervoltage output
condition. This can be avoided by using pulse-skipping
mode instead. When either channel is shut down, the POR
output is pulled low, since one or both of the channels are
not in regulation.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse-skipping mode, which provides the lowest
output ripple, at the cost of low current efficiency.
The LTC3548-2 can also be synchronized to an external
2.25MHz clock signal by the MODE/SYNC pin. During
synchronization, the mode is set to pulse-skipping and
the top switch turn-on is synchronized to the rising edge
of the external clock.
35482fb
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