LTC3418EUHF Просмотр технического описания (PDF) - Linear Technology
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LTC3418EUHF Datasheet PDF : 20 Pages
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LTC3418
APPLICATIONS INFORMATION
If we set the sum of R2 and R3 to 200k, then the following
equations can be solved.
R2 + R3 = 200k
1+
R2
R3
=
0.8V
0.67V
The two equations shown above result in the following
values for R2 and R3: R2 = 33.2k, R3 = 169k. The value
of R1 can now be determined by solving the equation:
1+
R1
202.2k
=
2.5V
0.8V
R1= 430k
A value of 432k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3418. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3418.
2. Connect the (+) terminals of the input capacitor(s), CIN,
as close as possible to the PVIN and PGND pins at all
four corners of the package. These capacitors provide
the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (PVIN, SVIN, VOUT, PGND, SGND or any other
DC rail in your system).
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and SGND.
6. To minimize switching noise coupling to SVIN, place
an optional local filter between SVIN and PVIN. Most
designs do not require this filter.
Top Layer
Figure 5. LTC3418 Layout Diagram
Bottom Layer
3418fb
15
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