LTC3418EUHF Просмотр технического описания (PDF) - Linear Technology
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LTC3418EUHF Datasheet PDF : 20 Pages
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LTC3418
APPLICATIONS INFORMATION
load currents can be misleading since the actual power
lost is of no consequence.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the Electrical Charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet
of charge dQ moves from VIN to ground. The resulting
dQ/dt is the current out of VIN that is typically larger
than the DC bias current. In continuous mode, IGATECHG
= f(QT + QB) where QT and QB are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to VIN and thus
their effects will be more pronounced at higher supply
voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I2R losses, simply add
RSW to RL and multiply the result by the square of the
average output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3418 does not dissipate much
heat due to its high efficiency.
But, in applications where the LTC3418 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3418 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise
is given by:
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature. For the 38-Lead 5mm × 7mm
QFN package, the θJA is 34°C/W.
The junction temperature, TJ, is given by:
TJ = TA + TR
where TA is the ambient temperature.
Note that at higher supply voltages, the junction temperature
is lower due to reduced switch resistance (RDS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an
amount equal to ΔILOAD(ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge
or discharge COUT generating a feedback error signal
used by the regulator to return VOUT to its steady-state
value. During this recovery time, VOUT can be monitored
for overshoot or ringing that would indicate a stability
problem. The ITH pin external components and output
capacitor shown in the Typical Application on the front
page of this data sheet will provide adequate compensa-
tion for most applications.
Design Example
As a design example, consider using the LTC3418 in an
application with the following specifications: VIN = 3.3V,
VOUT = 2.5V, IOUT(MAX) = 8A, IOUT(MIN) = 200mA, f = 1MHz.
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