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LTC1983ES6-3

100mA Regulated Charge-Pump Inverters in ThinSOT

Linear Technology 

LTC1983-3/LTC1983-5

U

OPERATIO (Refer to Block Diagram)

Inrush Currents

During normal operation, VIN will experience current tran-

sients in the several hundred milliamp range whenever the

charge pump is enabled. During start-up, these inrush

currents may approach 1 to 2 amps. For this reason, it is

important to minimize the source resistance between the

input supply and the VIN pin. Too much source resistance

may result in regulation problems or even prevent start-

up. One way that this can be avoided (especially when the

source impedance can’t be lowered due to system con-

straints) is to use a large VIN capacitor with low ESR right

at the VIN pin. If ceramic capacitors are used, you may

need to add 1µF to 10µF tantalum capacitor in parallel to

limit input voltage transients. Input voltage transients will

occur if VIN is applied via a switch or a plug. One example

of this situation is in USB applications.

VIN

CIN

10µF

TANTALUM

3.3V TO 5.5V LTC1983-3

VIN SHDN

FROM MPU

SHDN

GND VOUT –3V ± 4% COUT

10µF

C+

C–

CERAMIC

CFLY

1µF

CERAMIC

SHDN PIN WAVEFORMS:

LOW IQ MODE

(IOUT ≤ 100µA)

VOUT LOAD ENABLE MODE

(IOUT = 100µA TO 100mA)

(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)

1983 F02

Figure 2. Ultralow Quiescent Current Regulated Supply

Ultralow Quiescent Current Regulated Supply

The LTC1983 contains an internal resistor divider (refer to

the Block Diagram) that draws only 1µA (typ for the 3V

version) from VOUT during normal operation. During shut-

down, the resistor divider is disconnected from the output

and the part draws only leakage current from the output.

During no-load conditions, applying a 1Hz to 100Hz, 2%

to 5% duty cycle signal to the SHDN pin ensures that the

circuit of Figure 2 comes out of shutdown frequently

enough to maintain regulation even under low-load condi-

tions. Since the part spends nearly all of its time in

shutdown, the no-load quiescent current is essentially

zero. However, the part will still be in operation during the

time the SHDN pin is high, so the current will not be zero

and can be calculated using the following equations to

determine the approximate maximum current: IIN(MAX) =

[(Time out of shutdown) • (Burst Mode operation quies-

cent current) + (Normal operating IIN) • (Time output is

being charged before the LTC1983 enters Burst Mode

operation)]/(Period of SHDN signal). This number will be

highly dependent on the amount of board leakage current

and how many devices are connected to VOUT (each will

draw some leakage current) and must be calculated and

verified for each different board design.

The LTC1983 must be out of shutdown for a minimum

duration of 200µs to allow enough time to sense the output

and keep it in regulation. A 1Hz, 2% duty cycle signal will

keep VOUT in regulation under no-load conditions. Even

though the term no-load is used, there will always be board

leakage current and leakage current drawn by anything

connected to VOUT. This is why it is necessary to wake the

part up every once in a while to verify regulation. As the

VOUT load current increases, the frequency with which the

part is taken out of shutdown must also be increased to

prevent VOUT from drooping below the – 2.88V (for the 3V

version) during the OFF phase (see Figure 3). A 100Hz, 2%

duty cycle signal on the SHDN pin ensures proper regula-

tion with load currents as high as 100µA. When load

current greater than 100µA is needed, the SHDN pin must

be forced high as in normal operation.

Each time the LTC1983 comes out of shutdown, the part

delivers a minimum of one clock cycle worth of charge to

the output. Under high VIN (>4V) and/or low IOUT (<10µA)

conditions, this behavior may cause a net excess of charge

to be delivered to the output capacitor if a high frequency

signal is used on the SHDN pin (e.g., 50Hz to 100Hz).

Under such conditions, VOUT will slowly drift positive and

may even go out of regulation. To avoid this potential

1983fa

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