LTC1726IS8-2.5(RevB) Просмотр технического описания (PDF) - Linear Technology

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производитель

LTC1726IS8-2.5
(Rev.:RevB)

Triple Supply Monitor and µP Supervisor with Adjustable Reset and Watchdog Timer

Linear Technology 

LTC1726

APPLICATIO S I FOR ATIO

Figure 3 contains a simple circuit for 5V systems that can’t

risk the RST output going high in the 3.1V to 4.15V range

(possibly due to very slow rise time on the 5V supply).

Diode D1 powers the LTC1726-5 while dropping ≈ 0.6V

from the VCC5 pin to the VCC3 pin. This prevents the part’s

internal override circuit from being activated. Without the

override circuit active, the RST pin stays low until VCC5

reaches VRT5 ≅ 4.675V. (See Figure 4.)

5V

0.1µF

D1

LTC1726-5

1

VCC3

2

VCC5

3

6

VCCA

RST

4

GND

R1

10k

TO SYSTEM

RESET

1726 F03

D1: MMBD914 OR EQUIVALENT

PINS 5, 7 AND 8 NOT SHOWN FOR CLARITY

Figure 3. LTC1726-5 Monitoring a Single 5V

Supply. D1 Used to Avoid RST High Near 3.1V

to 4V (See Figure 2).

5

VCC5 = VCCA = 0V TO 5V

10k PULL-UP FROM RST TO VCC5

4 TA = 25°C

3

2

1

LTC1726-2.5 Override Functions

The VCCA pin, if unused, can be tied to either VCC3 or VCC25.

This is an obvious solution since the trip points for VCC3

and VCC25 will always be greater than the trip point for

VCCA. Likewise, the VCC25, if unused, can be tied to VCC3.

VCC3 must always be used. Tying VCC3 to VCC25 and

operating off of a 2.5V supply will result in the continuous

assertion of RST.

Watchdog Timer

The watchdog circuit monitors a µP’s activity. The µP is

required to change the logic state of the WDI pin on a

periodic basis in order to clear the watchdog timer and

prevent the LTC1726 from issuing a reset.

During power-up, the watchdog timer remains cleared

while reset is asserted. As soon as the reset timer times out,

the watchdog timer is started. The watchdog timer will

continue to run until a transition is detected on the WDI

input or until the watchdog timer times out. Once the

watchdog timer times out, the internal circuitry asserts the

reset and starts the reset timer. When the reset timer times

out and reset is deasserted, the watchdog timer is again

started. If no WDI transition is received within the watchdog

time-out period, the reset will be reasserted at the end of the

watchdog time-out period. If a transition is received on the

WDI input during the watchdog time-out period, the watch-

dog timer will be restarted and reset will remain deasserted.

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VCC5 (V)

1726 F04

Figure 4. RST Output Voltage

Characteristics of the Circuit in Figure 3

1726fb

8

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