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LTC1430A

High Power Step-Down Switching Regulator Controller

Linear Technology 

LTC1430A

APPLICATI S I FOR ATIO

scheme. In 5V input designs where an auxiliary 12V supply

is available to power PVCC1 and PVCC2, standard MOSFETs

with RDS(ON) specified at VGS = 5V or 6V can be used with

good results. The current drawn from this supply varies

with the MOSFETs used and the LTC1430A’s operating

frequency, but is generally less than 50mA.

LTC1430A designs that use a doubler charge pump to

generate gate drive for Q1 and run from PVCC voltages

below 7V cannot provide enough gate drive voltage to fully

enhance standard power MOSFETs. When run from 5V, a

doubler circuit may work with standard MOSFETs, but the

MOSFET RON may be quite high, raising the dissipation in

the FETs and costing efficiency. Logic level FETs are a

better choice for 5V PVCC systems; they can be fully

enhanced with a doubler charge pump and will operate at

maximum efficiency. Doubler designs running from PVCC

voltages near 4V will begin to run into efficiency problems

even with logic level FETs; such designs should be built

with tripler charge pumps (see Figure 7) or with newer,

super low threshold MOSFETs. Note that doubler charge

pump designs running from more than 7V and all tripler

charge pump designs should include a zener clamp diode

DZ at PVCC1 to prevent transients from exceeding the

absolute maximum rating at that pin.

Once the threshold voltage has been selected, RON should

be chosen based on input and output voltage, allowable

power dissipation and maximum required output current.

In a typical LTC1430A buck converter circuit operating in

continuous mode, the average inductor current is equal to

DZ

12V

1N5242

1N5817

1N5817

PVCC

1N5817

10µF

PVCC2

PVCC1

G1

G2

LTC1430A

0.1µF

0.1µF

Q1

L1

Q2

VOUT

+

COUT

1430 • F07

Figure 7. Tripling Charge Pump

the output load current. This current is always flowing

through either Q1 or Q2 with the power dissipation split up

according to the duty cycle:

DC (Q1) =

VOUT

VIN

DC

(Q2)

=

1

–

VOUT

VIN

= (VIN – VOUT)

VIN

The RON required for a given conduction loss can now be

calculated by rearranging the relation P = I2R:

RON

(Q1)

=

PMAX(Q1)

DC(Q1)(IMAX2)

=

VIN(PMAX)(Q1)

VOUT(IMAX2)

RON

(Q2)

=

PMAX(Q2)

DC(Q2)(IMAX2)

=

VIN(PMAX)(Q2)

(VIN – VOUT)(IMAX2)

PMAX should be calculated based primarily on required

efficiency. A typical high efficiency circuit designed for 5V

in, 3.3V at 10A out might require no more than 3%

efficiency loss at full load for each MOSFET. Assuming

roughly 90% efficiency at this current level, this gives a

PMAX value of (3.3V)(10A/0.9)(0.03) = 1.1W per FET and

a required RON of:

RON

(Q1)

=

(5V)(1.1W)

(3.3V)(10A2)

=

0.017Ω

RON

(Q2)

=

(5V)(1.1W)

(5V – 3.3V)(10A2)

=

0.032Ω

Note that the required RON for Q2 is roughly twice that of

Q1 in this example. This application might specify a single

0.03Ω device for Q2 and parallel two more of the same

devices to form Q1. Note also that while the required RON

values suggest large MOSFETs, the dissipation numbers

10

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