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LTC1277 Просмотр технического описания (PDF) - Linear Technology

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LTC1277 Datasheet PDF : 20 Pages
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LTC1274/LTC1277
BLOCK DIAGRA S
AIN
VREF
REFRDY
AGND
DGND
2.42V REF
INTERNAL
CLOCK
LTC1274
CSAMPLE
ZEROING SWITCHES
12-BIT CAPACITIVE DAC
COMPARATOR
VDD
VSS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
12
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
SLEEP CONVST RD
CS BUSY
OUTPUT LATCHES
•••
D11
D0
LTC1274 • BD
AIN+
AIN–
VREF
REFRDY
AGND
DGND
2.42V REF
LTC1277
CSAMPLE
ZEROING SWITCHES
12-BIT CAPACITIVE DAC
COMPARATOR
VDD
VSS
(0V FOR UNIPOLAR MODE OR
–5V FOR BIPOLAR MODE)
INTERNAL
CLOCK
12
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
HBEN SLEEP NAP CONVST RD CS BUSY
OUTPUT LATCHES
•••••
D7
D1/9
D0/8
VLOGIC
3V OR 5V
LTC1277 • BD
TEST CIRCUITS
Load Circuits for Access Timing
5V
3k
DBN
DBN
3k
CL
CL
DGND
A) HIGH-Z TO VOH (t9)
AND VOL TO VOH (t6)
DGND
B) HIGH-Z TO VOL (t9)
AND VOH TO VOL (t6)
1274/77 • TC01
Load Circuits for Output Float Delay
5V
DBN
3k
DBN
10pF
3k
10pF
DGND
A) VOH TO HIGH-Z
DGND
B) VOL TO HIGH-Z
1274/77 • TC02
9

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