LTC1273(Rev0) Просмотр технического описания (PDF) - Linear Technology

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LTC1273
(Rev.:Rev0)

12-Bit, 300ksps Sampling A/D Converters with Reference

Linear Technology 

LTC1273

LTC1275/LTC1276

APPLICATI S I FOR ATIO

CONVERSION DETAILS

The LTC1273/LTC1275/LTC1276 use a successive ap-

proximation algorithm and an internal sample-and-hold

circuit to convert an analog signal to a 12-bit parallel or

2-byte output. The ADCs are complete with a precision

reference and an internal clock. The control logic provides

easy interface to microprocessors and DSPs. (Please refer

to the Digital Interface section for the data format.)

Conversion start is controlled by the CS, RD and HBEN

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset and the three-state data

outputs are enabled. Once a conversion cycle has begun

it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the AIN input connects to the sample-and-hold

capacitor during the acquire phase, and the comparator

offset is nulled by the feedback switch. In this acquire

phase, a minimum delay of 600ns will provide enough

time for the sample-and-hold capacitor to acquire the

analog signal. During the convert phase, the comparator

feedback switch opens, putting the comparator into the

compare mode. The input switch switches CSAMPLE to

ground, injecting the analog input charge onto the sum-

ming junction. This input charge is successively com-

pared with the binary-weighted charges supplied by the

capacitive DAC. Bit decisions are made by the high speed

comparator. At the end of a conversion, the DAC output

balances the AIN input charge. The SAR contents (a 12-bit

data word) which represent the AIN are loaded into the

12-bit output latches.

DYNAMIC PERFORMANCE

The LTC1273/LTC1275/LTC1276 have an exceptionally

high speed sampling capability. FFT (Fast Fourier Trans-

form) test techniques are used to characterize the ADC’s

frequency response, distortion and noise at the rated

throughput. By applying a low distortion sine wave and

analyzing the digital output using an FFT algorithm, the

ADC’s spectral content can be examined for frequencies

outside the fundamental. Figure 2 shows a typical LTC1275

FFT plot.

Signal-to-Noise Ratio

The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the

ratio between the RMS amplitude of the fundamental input

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

to frequencies from above DC and below half the sampling

frequency. Figure 2 shows a typical spectral content with

a 300kHz sampling rate and a 29kHz input. The dynamic

performance is excellent for input frequencies up to the

Nyquist limit of 150kHz.

SAMPLE

AIN

HOLD

CSAMPLE

CDAC

DAC

VDAC

SAMPLE

SI

–

+

COMPARATOR

S

A

R

LTC1273/75/76 • F01

12-BIT

LATCH

Figure 1. AIN Input

0

fSAMPLE = 300kHz

fIN = 29.37kHz

– 20

– 40

– 60

– 80

– 100

– 120

0 20 40 60 80 100 120 140 160

FREQUENCY (kHz)

LTC1273/75/76 • F02

Figure 2. LTC1275 Nonaveraged, 1024 Point FFT Plot

10

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