LTC1272-3ACSW Просмотр технического описания (PDF) - Linear Technology
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LTC1272-3ACSW Datasheet PDF : 20 Pages
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LTC1272
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
LTC1272-XA/C
MIN TYP MAX
UNITS
t1
CS to RD Setup Time
t2
RD to BUSY Delay
CL = 50pF
COM Grade
●
0
ns
80
190
ns
●
230
ns
t3
Data Access Time After RD↓
CL = 20pF
COM Grade
50
90
ns
●
110
ns
CL = 100pF
COM Grade
70
125
ns
●
150
ns
t4
RD Pulse Width
t5
CS to RD Hold Time
t6
Data Setup Time After BUSY
COM Grade
COM Grade
t3
ns
●
t3
ns
●
0
ns
40
70
ns
●
90
ns
t7
Bus Relinquish Time
COM Grade
20
30
75
ns
● 20
85
ns
t8
HBEN to RD Setup Time
t9
HBEN to RD Hold Time
t10
Delay Between RD Operations
t11
Delay Between Conversions
t12
Aperture Delay of Sample and Hold
t13
CLK to BUSY Delay
Jitter < 50ps
COM Grade
●
0
ns
●
0
ns
● 200
ns
1
µs
25
ns
80
170
ns
●
220
ns
tCONV
Conversion Time
● 12
13
CLK
CYCLES
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together, unless otherwise noted.
Note 3: When the analog input voltage is taken below ground it will be
clamped by an internal diode. This product can handle, with no external
diode, input currents of greater than 60mA below ground without latch-up.
Note 4: VDD = 5V, fCLK = 4MHz for LTC1272-3, and 1.6MHz for
LTC1272-8, tr = tf = 5ns unless otherwise specified. For best analog
performance, the LTC1272 clock should be synchronized to the RD and
CS control inputs with at least 40ns separating convert start from the
nearest clock edge.
Note 5: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 6: The LTC1272 has the same 0V to 5V input range as the AD7572
but, to achieve single supply operation, it provides a 2.42V reference
output instead of the –5.25V of the AD7572. This requires that the polarity
of the reference bypass capacitor be reversed when plugging an LTC1272
into an AD7572 socket.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 5V. Timing specifications are sample tested at 25°C to
ensure compliance. All input control signals are specified with tr = tf = 5ns
(10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13
through 17.
1272fb
4
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