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LT3959

Wide Input Voltage Range Boost/SEPIC/Inverting Converter with 6A, 40V Switch

Linear Technology 

LT3959

Applications Information

INTVCC Low Dropout Voltage Regulators

The LT3959 features two internal low dropout (LDO) volt-

age regulators (VIN LDO and DRIVE LDO) powered from

different supplies (VIN and DRIVE respectively). Both LDO’s

regulate the internal INTVCC supply which powers the gate

driver and the internal loads, as shown in Figure 1. Both

regulators are designed so that current does not flow from

INTVCC to the LDO input under a reverse bias condition.

DRIVE LDO regulates the INTVCC to 4.75V, while VIN LDO

regulates the INTVCC to 3.75V. VIN LDO is turned off when

the INTVCC voltage is greater than 3.75V (typical). Both

LDO’s can be turned off if the INTVCC pin is driven by a

supply of 4.75V or higher but less than 8V (the INTVCC

maximum voltage rating is 8V). A table of the LDO sup-

ply and output voltage combination is shown in Table 1.

Table 1. LDO’s Supply and Output Voltage Combination (Assuming

That the LDO Dropout Voltage is 0.15V)

SUPPLY VOLTAGES

LDO OUTPUT

VIN

VIN ≤ 3.9V

3.9V < VIN ≤ 40V

DRIVE

VDRIVE < VIN

VDRIVE = VIN

VIN < VDRIVE < 4.9V

4.9V ≤ VDRIVE ≤ 40V

VDRIVE < 3.9V

VDRIVE = 3.9V

3.9V < VDRIVE < 4.9V

4.9V ≤ VDRIVE ≤ 40V

INTVCC

VIN – 0.15V

VIN – 0.15V

VDRIVE – 0.15V

4.75V

3.75V

3.75V

VDRIVE – 0.15V

4.75V

LDO STATUS

(Note 7)

#1 Is ON

#1 #2 are ON

#2 Is ON

#2 Is ON

#1 Is ON

#1 #2 are ON

#2 Is ON

#2 Is ON

Note 7: #1 is VIN LDO and #2 is DRIVE LDO

The DRIVE pin provides flexibility to power the gate driver

and the internal loads from a supply that is available only

when the switcher is enabled and running. If not used,

the DRIVE pin should be tied to VIN.

The INTVCC pin must be bypassed to SGND immediately

adjacent to the INTVCC pin with a minimum of 4.7µF ceramic

capacitor. Good bypassing is necessary to supply the high

transient currents required by the MOSFET gate driver.

Operating Frequency and Synchronization

The choice of operating frequency may be determined

by on-chip power dissipation, otherwise it is a trade-off

between efficiency and component size. Low frequency op-

eration improves efficiency by reducing gate drive current

and internal MOSFET and diode switching losses. However,

lower frequency operation requires a physically larger

inductor. Switching frequency also has implications for

loop compensation. The LT3959 uses a constant-frequency

architecture that can be programmed over a 100kHz to

1MHz range with a single external resistor from the RT

pin to SGND, as shown in Figure 1. The RT pin must have

an external resistor to SGND for proper operation of the

LT3959. A table for selecting the value of RT for a given

operating frequency is shown in Table 2.

Table 2. Timing Resistor (RT) Value

OSCILLATOR FREQUENCY (kHz)

100

200

300

400

500

600

700

800

900

1000

RT (kΩ)

86.6

41.2

27.4

21.0

16.5

13.7

11.5

9.76

8.45

6.81

The switching frequency of the LT3959 can be synchro-

nized to the positive edge of an external clock source.

By providing a digital clock signal into the SYNC pin,

the LT3959 will operate at the SYNC clock frequency. If

this feature is used, an RT resistor should be chosen to

program a switching frequency 20% slower than SYNC

pulse frequency. The SYNC pulse should have a minimum

pulse width of 200ns. Tie the SYNC pin to SGND if this

feature is not used.

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For more information www.linear.com/LT3959

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