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LT3761

60 VIN LED Controller with Internal PWM Generator

Linear Technology 

LT3761

Pin Functions

between current sense inputs ISP and ISN is less than

25mV. To function, the pin requires an external pull-up

resistor, usually to INTVCC. When the PWM input is low

and the DC/DC converter is idle, the OPENLED condition

is latched to the last valid state when the PWM input was

high. When PWM input goes high again, the OPENLED

pin will be updated. This pin may be used to report transi-

tion from constant current regulation to constant voltage

regulation modes, for instance in a charger or current

limited voltage supply.

DIM/SS (Pin 10): Soft-Start and PWMOUT Dimming Signal

Generator Programming Pin. This pin modulates switching

regulator frequency and compensation pin voltage (VC)

clamp when it is below 1V. The soft-start interval is set

with an external capacitor and the DIM/SS pin charging

current. The pin has an internal 12μA (typical) pull-up

current source. The soft-start pin is reset to GND by an

undervoltage condition (detected at the EN/UVLO pin),

INTVCC undervoltage, overcurrent event sensed at ISP/

ISN, or thermal limit. After initial start-up with EN/UVLO,

DIM/SS is forced low until the first PWM rising edge. When

DIM/SS reaches the steady-state voltage (~1.17V), the

charging current (sum of internal and external currents) is

sensed and used to set the PWM pin charging and discharge

currents and threshold hysteresis. In this manner, the SS

charging current sets the duty cycle of the PWMOUT signal

generator associated with the PWM pin. This pin should

always have a capacitor to GND, minimum 560pF value,

when used with the PWMOUT signal generator function.

Place the PWM pin capacitor close to the IC.

RT (Pin 11): Switching Frequency Adjustment Pin. Set the

frequency using a resistor to GND (for resistor values, see

the Typical Performance curve or Table 2). Do not leave

the RT pin open. Place the resistor close to the IC.

EN/UVLO (Pin 12): Enable and Undervoltage Detect Pin.

An accurate 1.22V falling threshold with externally pro-

grammable hysteresis causes the switching regulator to

shut down when power is insufficient to maintain output

regulation. Above the 1.24V (typical) rising enable threshold

(but below 2.5V), EN/UVLO input bias current is sub-μA.

Below the 1.22V (typical) falling threshold, an accurate

2.3μA (typical) pull-down current is enabled so the user

can define the rising hysteresis with the external resistor

selection. An undervoltage condition causes the GATE

and PWMOUT pins to transition low and resets soft-start.

Tie to 0.4V, or less, to disable the device and reduce VIN

quiescent current below 1μA.

INTVCC (Pin 13): Current limited, low dropout linear regula-

tor regulates to 7.85V (typical) from VIN. Supplies internal

loads, GATE and PWMOUT drivers. Must be bypassed with

a 1µF ceramic capacitor placed close to the pin and to the

exposed pad GND of the IC.

VIN (Pin 14): Power Supply for Internal Loads and INTVCC

Regulator. Must be locally bypassed with a 0.22µF (or

larger) low ESR capacitor placed close to the pin.

SENSE (Pin 15): The Current Sense Input for the Switch

Control Loop. Kelvin connect the SENSE pin to the positive

terminal of the switch current sense resistor in the source

of the external power NFET. The negative terminal of the

switch current sense resistor should be Kelvin connected

to the exposed pad (GND) of the LT3761.

GATE (Pin 16): N-channel FET Gate Driver Output. Switches

between INTVCC and GND. Driven to GND during shutdown,

fault or idle states.

GND (Exposed Pad Pin 17): Ground. This pin also serves

as current sense input for the control loop, sensing the

negative terminal of the current sense resistor. Solder the

exposed pad directly to the ground plane.

3761f

9

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