LT3579IUFD-1-PBF Просмотр технического описания (PDF) - Linear Technology
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LT3579IUFD-1-PBF Datasheet PDF : 40 Pages
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LT3579/LT3579-1
APPLICATIONS INFORMATION
Inverting Topology Specific Layout Guidelines
• Keep ground return path from the cathode of D1 (to
chip) separated from output capacitor COUT’s ground
return path (to chip) in order to minimize switching
noise coupling into the output. Notice the separate
ground return for D1’s cathode in Figure 11.
• Keep length of loop (high speed switching path)
governing switch, flying capacitor C1, diode D1, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
THERMAL CONSIDERATIONS
For the LT3579 to deliver its full output power, it is imp-
erative that a good thermal path be provided to dissipate
the heat generated within the package. This can be
accomplished by taking advantage of the thermal pad on
the underside of the IC. It is recommended that multiple
vias in the printed circuit board be used to conduct heat
away from the IC and into a copper plane with as much
area as possible.
Power & Thermal Calculations
Power dissipation in the LT3579 chip comes from four
primary sources: switch I2R loss, NPN base drive loss
(AC), NPN base drive loss (DC), and additional VIN pin
current. These formulas assume continuous mode
operation, so they should not be used for calculating
thermal losses or efficiency in discontinuous mode or at
light load currents.
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GND
CIN
–
VIN
1
21
20
2
19
3
18
4
17
5
16
6
15
7
14
A8
9
13 B
12
10
11
+
C1
D1
L1
L2
SYNC
SHDN
CLKOUT
COUT
–
VOUT
+
3579 F10
A– RETURN CIN AND L2 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN COUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2 –MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.
Figure 10. Suggested Component Placement for SEPIC Topology in FE20 Package
35791f
17
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