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LT3513

2MHz High Current 5-Output Regulator for TFT-LCD Panels

Linear Technology 

LT3513

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

LDO Current Limit vs Temperature

9

8

7

6

5

4

3

2

1

0

–50 –25 0 25 50 75 100 125

AMBIENT TEMPERATURE (°C)

3513 G19

VUVLO vs Temperature

1.33

1.32

UVLO FOR

1.31

START

1.30

UVLO MINIMUM

1.29

FOR RUN

1.28

1.27

1.26

–50

0

50

100

AMBIENT TEMPERATURE (oC)

3513 G20

Reference Voltage for FB5, LDO

670

660

650

640

630

620

610

600

–40 –15

10 35 60 85

TEMPERATURE (°C)

110

3513 G21

PIN FUNCTIONS

FB5 (Pin 1): Feedback Pin. Tie the resistor tap to this pin

and set the output of the LDO according to VLDO = 0.625 •

(1 + R14/R15). Reference designators refer to Figure 1.

VC1 (Pin 2): Control Voltage and Compensation Pin for

Internal Error Amplifier. Connect a series RC from this pin

to ground to compensate switching regulator 1.

RUN-SS3/4 (Pin 3): Run/Soft-Start Pin. This is the soft-

start pin for switching regulators 3 and 4. Place a soft-start

capacitor here to limit start-up inrush current and output

voltage ramp rate. When the BIAS pin reaches 2.8V, a 2μA

current source charges the capacitor. When the voltage at

this pin reaches 0.8V, switches 3 and 4 turn on and begin

switching. For slower start-up use a larger capacitor. For

complete shutdown tie RUN-SS3/4 to ground.

FB3 (Pin 4): Feedback Pin. Tie the resistor tap to this

pin and set VON according to VON = 1.23V • (1 + R8/R9)

– 150mV. Reference designators refer to Figure 1.

RUN-SS2 (Pin 5): Run/Soft-Start Pin. This is the soft-start

pin for switching regulator 2. Place a soft-start capacitor

here to limit start-up inrush current and output voltage

ramp rate. When the BIAS pin reaches 2.25V, a 2μA cur-

rent source charges the capacitor. When the voltage at this

pin reaches 0.8V, switch 2 turns on and begins switching.

For slower start-up use a larger capacitor. For complete

shutdown tie RUN-SS2 to ground.

SW3 (Pin 6): Switch Node. The SW3 pin is the collector of

the internal NPN bipolar transistor for switching regulator

3. Minimize trace area at this pin to keep EMI down.

E3 (Pin 7): This is switching regulator 3’s output and

the emitter of the output disconnect PNP. Tie the output

capacitor and resistor divider here.

VON (Pin 8): This is the delayed output for switching

regulator 3. VON reaches its programmed voltage after the

internal CT timer times out. Protection circuitry ensures

VON is disabled if any of the four outputs are more than

10% below normal voltage. This output is also disabled

when VON_CLK is high.

VONSINK (Pin 9): This is an open-collector output con-

trolled by the VON_CLK pin. When VON_CLK is low, this

pin draws no current and when VON_CLK is high, this pin

draws current.

VON_CLK (Pin 10): This pin controls the output disconnect

device and the open collector of VONSINK. When this pin is

low, the VON pin is enabled and the VONSINK pin is a high

impedance. When this pin is high, the VON pin is disabled

and the VONSINK pin sinks current to ground.

3513fa

7

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