LT3150 Просмотр технического описания (PDF) - Linear Technology

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LT3150

Fast Transient Response, Low Input Voltage, Very Low Dropout Linear Regulator Controller

Linear Technology 

LT3150

PI FU CTIO S

VIN2 (Pin 5): This is the input supply for the linear regulator

control circuitry and provides sufficient gate drive compli-

ance for the external N-channel MOSFET. The maximum

operating VIN2 is 20V and the minimum operating VIN2 is

set by VOUT + (VGS of the MOSFET at max IOUT) + 1.6V

(worst-case VIN2 to GATE output swing).

GND (Pin 6): Analog Ground. This pin is also the negative

sense terminal for the internal 1.21V reference. Connect the

LDO regulator external feedback divider network and fre-

quency compensation components that terminate to GND

directly to this pin for best regulation and performance. Also,

tie this pin directly to SWGND (Pin 2) and GND (Pin 15).

NC (Pins 7, 10): No Connect.

FB2 (Pin 8): This is the inverting input of the error amplifier

for the linear regulator. The noninverting input is tied to the

internal 1.21V reference. Input bias current for this pin is

typically 0.6µA flowing out of the pin. Tie this pin to a

resistor divider network to set output voltage. Tie the top

of the external resistor divider directly to the output load

for best regulation performance.

COMP (Pin 9): This is the high impedance gain node of the

error amplifier and is used for external frequency compen-

sation. The transconductance of the error amplifier is 15

millimhos and open-loop voltage gain is typically 84dB.

Frequency compensation is generally performed with a

series RC + C network to ground.

GATE (Pin 11): This is the output of the error amplifier

that drives N-channel MOSFETs with up to 5000pF of

“effective” gate capacitance. The typical open-loop out-

put impedance is 2Ω. When using low input capacitance

MOSFETs (< 1500pF), a small gate resistor of 2Ω to 10Ω

dampens high frequency ringing created by an LC reso-

nance due to the MOSFET gate’s lead inductance and

input capacitance. The GATE pin delivers up to 50mA for

a few hundred nanoseconds when slewing the gate of the

N-channel MOSFET in response to output load current

transients.

INEG (Pin 12): This is the negative sense terminal of the

current limit amplifier. A small sense resistor is connected

in series with the drain of the external MOSFET and is

connected between the IPOS and INEG pins. A 50mV

threshold voltage in conjunction with the sense resistor

value sets the current limit level. The current sense resis-

tor can be a low value shunt or can be made from a piece

of PC board trace. If the current limit amplifier is not used,

tie the INEG pin to IPOS to defeat current limit. An alternative

is to ground the INEG pin. This action disables the current

limit amplifier and additional internal circuitry activates

the timer circuit on the SHDN2 pin if the GATE pin swings

to the VIN rail. This option provides the user with a

No RSENSETM current limit function.

IPOS (Pin 13): This is the positive sense terminal of the

current limit amplifier. Tie this pin directly to the main

input voltage from which the output voltage is regulated.

SHDN1 (Pin 14): Boost Regulator Shutdown Pin. Tie to 1V

or more to enable device. Ground to shut down. This pin

must not float for proper operation. Connect SHDN1

externally as it does not incorporate an internal pull-up or

pull-down.

GND (Pin 15): Boost Converter Analog Ground. This pin

is also the negative sense terminal for the FB1 1.23V

reference. Connect the external feedback divider net-

work, which sets the VIN2 supply voltage and terminates

to GND, directly to this pin for best regulation and

performance. Also, tie this pin directly to SWGND (Pin 2)

and GND (Pin 6).

FB1 (Pin 16): Boost Regulator Feedback Pin. Reference

voltage is 1.23V. Connect resistive divider tap here.

Minimize trace area at FB1. Set VOUT = VIN2 according to

VOUT = 1.23V(1 + R1/R2).

No RSENSE is a trademark of Linear Technology Corporation.

3150f

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