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LT3011

50mA, 3V to 80V Low Dropout Micropower Linear Regulator with PWRGD

Linear Technology 

LT3011

APPLICATIONS INFORMATION

in a small package, but they tend to have strong voltage

and temperature coefficients, as shown in Figures 2 and 3.

When used with a 5V regulator, a 16V 10μF Y5V capacitor

can exhibit an effective value as low as 1μF to 2μF for the

DC bias voltage applied and over the operating tempera-

ture range. The X5R and X7R dielectrics result in more

stable characteristics and are more suitable for use as the

output capacitor. The X7R type has better stability across

temperature, while the X5R is less expensive and is avail-

able in higher values. Care still must be exercised when

using X5R and X7R capacitors; the X5R and X7R codes

only specify operating temperature range and maximum

capacitance change over temperature. Capacitance change

due to DC bias with X5R and X7R capacitors is better than

Y5V and Z5U capacitors, but can still be significant enough

to drop capacitor values below appropriate levels. Capaci-

tor DC bias characteristics tend to improve as component

case size increases, but expected capacitance at operating

voltage should be verified.

Voltage and temperature coefficients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress, simi-

lar to the way piezoelectric accelerometer or microphone

works. For a ceramic capacitor, the stress can be induced

by vibrations in the system or thermal transients.

PWRGD Flag and Timing Capacitor Delay

The PWRGD flag is used to indicate that the ADJ pin volt-

age is within 10% of the regulated voltage. The PWRGD

pin is an open-collector output, capable of sinking 50μA

of current when the ADJ pin voltage is low. There is no

internal pull-up on the PWRGD pin; an external pull-up

resistor must be used. When the ADJ pin rises to within

10% of its final reference value, a delay timer is started.

At the end of this delay, programmed by the value of the

capacitor on the CT pin, the PWRGD pin switches to a high

impedance and is pulled up to a logic level by an external

pull-up resistor.

To calculate the capacitor value on the CT pin, use the

following formula:

CTIME

=

ICT • tDELAY

VCT(HIGH) − VCT(LOW)

Figure 4 shows a block diagram of the PWRGD circuit. At

start-up, the timing capacitor is discharged and the PWRGD

pin will be held low. As the output voltage increases and

the ADJ pin crosses the 90% threshold, the JK flipflop is

reset, and the 3μA current source begins to charge the

timing capacitor. Once the voltage on the CT pin reaches

the VCT(HIGH) threshold (approximately 1.7V at 25°C), the

capacitor voltage is clamped and the PWRGD pin is set to

a high impedance state.

20

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10MF

0

X5R

–20

–40

–60

Y5V

–80

–100

0 2 4 6 8 10 12 14 16

DC BIAS VOLTAGE (V)

3011 F02

Figure 2. Ceramic Capacitor DC Bias Characteristics

10

40

20

0

X5R

–20

–40

Y5V

–60

–80

BOTH CAPACITORS ARE 16V,

–100 1210 CASE SIZE, 10MF

–50 –25 0 25 50 75

TEMPERATURE (oC)

100 125

3011 F03

Figure 3. Ceramic Capacitor Temperature Characteristics

3011f

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