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LT1186F

DAC Programmable CCFL Switching Regulator (Bits-to-Nits™)

Linear Technology 

LT1186F

PIN FUNCTIONS

AGND (Pin 5): This is the low current analog ground. It is

the negative sense terminal for the internal 1.24V refer-

ence and the ICCFL summing voltage in the LT1186F.

Connect low current signal paths that terminate to ground

and frequency compensation components that terminate

to ground directly to this pin for best regulation and

performance.

SHDN (Pin 6): Pulling this pin low causes complete

regulator shutdown with quiescent current typically re-

duced to 35µA. If the pin is not used, use a pull-up resistor

to force a logic high level (maximum of 6V) or tie directly

to VCC. In a shutdown condition, the DAC retains its last

output current setting and returns to this level when the

logic-low signal at the shutdown pin is removed.

CLK (Pin 7): This pin is the shift clock for the DAC. This

clock synchronizes the serial data and is a Schmitt

trigger input. In standard SPI mode, the clock shifts data

into DIN and out of DOUT on the rising and falling edges

of the clock respectively. In pulse mode, the rising edge

of the clock either increments or decrements the counter.

This action depends on the choice of a 1-wire interface

(increment only) or a 2-wire interface (increment/decre-

ment).

CS (Pin 8): This pin is the chip select input for the DAC. In

SPI mode, a logic low on the CS pin enables the DAC to

receive and transfer 8-bit serial data. After the serial input

data is shifted in, a rising edge of CS transfers the data into

the counter, the DAC assumes the new IOUT value and the

DOUT pin returns to the high impedance state. On power

up, a logic high places the DAC into pulse mode. Pulling CS

low after this places the DAC into SPI mode until VCC

resets.

DIN or UP/DN (Pin 9): This pin is the digital input for the

DAC. In SPI mode, the 8-bit serial data is shifted into the

DIN input on each rising edge of the clock signal. In pulse

mode, on power up, a logic high at DIN transfers the pin

function from DIN to UP/DN, puts the counter into incre-

ment-only mode and the pin function shifts to up or down

increment control of DAC output current. If UP/DN re-

ceives a logic-low signal, the counter configures to incre-

ment/decrement mode until VCC resets.

DOUT (Pin 10): This pin is the digital output for the DAC. In

SPI mode, DOUT is in three-state until CS falls low. The

DOUT pin then serially transfers the previous 8-bit data on

every falling edge of the clock. When CS rises high again,

DOUT returns to a three-state condition. In pulse mode,

DOUT is always three-stated.

IOUT (Pin 11): This pin is the analog current output for the

DAC and provides an output current of 50 ±3µA over

temperature. This pin can be biased from – 20V to 2V for

a 3.3V VCC supply voltage or from – 20V to 2.5V for a 5V

VCC supply voltage. However, this pin is tied to the ICCFL pin

and provides the programming current which sets operat-

ing lamp current. The IOUT pin has very little bias voltage

change when it is tied to the ICCFL pin as ICCFL is regulated.

The programming current is sourced from the IOUT pin and

sunk by the ICCFL pin.

VCC (Pin 12): This is the supply pin for the LT1186F. The

IC accepts an input voltage range of 3V minimum to 6.5V

maximum with little change in quiescent current (zero

switch current). An internal, low-dropout regulator pro-

vides a 2.4V supply for most of the internal circuitry.

Supply current increases as switch current increases at a

rate approximately 1/50 of switch current. This corre-

sponds to a forced Beta of 50 for the power switch. The IC

incorporates undervoltage lockout by sensing regulator

dropout and locking out switching for input voltages

below 2.5V. Hysteresis is not used to maximize the useful

range of input voltage. The typical input voltage is a 3.3V

or 5V logic supply.

ROYER (Pin 13): This pin connects to the center-tapped

primary of the Royer converter and is used with the BAT

pin in a floating-lamp configuration where lamp current is

controlled by sensing Royer primary-side converter cur-

rent. This pin is the inverting terminal of a high-side

current sense amplifier. The typical quiescent current is

50µA into the pin. If the CCFL regulator is not used in a

floating-lamp configuration, tie the Royer and BAT pins

together.

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