LPC2146FBD64 Просмотр технического описания (PDF) - NXP Semiconductors.

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LPC2146FBD64

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC

NXP Semiconductors. 

NXP Semiconductors

Table 3. Pin description …continued

Symbol

Pin

Type

P1.23/

PIPESTAT2

36[6]

I/O

O

P1.24/

TRACECLK

32[6]

I/O

O

P1.25/EXTIN0

28[6]

I/O

I

P1.26/RTCK

24[6]

I/O

I/O

P1.27/TDO

P1.28/TDI

P1.29/TCK

P1.30/TMS

P1.31/TRST

D+

D

RESET

XTAL1

XTAL2

RTCX1

RTCX2

VSS

VSSA

VDD

64[6]

I/O

O

60[6]

I/O

I

56[6]

I/O

I

52[6]

I/O

I

20[6]

I/O

I

10[7]

I/O

11[7]

I/O

57[8]

I

62[9]

I

61[9]

O

3[9][10]

I

5[9][10]

O

6, 18, 25, 42, I

50

59

I

23, 43, 51 I

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

Description

P1.23 — General purpose input/output digital pin (GPIO). Standard

I/O port with internal pull-up.

PIPESTAT2 — Pipeline Status, bit 2.

P1.24 — General purpose input/output digital pin (GPIO). Standard

I/O port with internal pull-up.

TRACECLK — Trace Clock.

P1.25 — General purpose input/output digital pin (GPIO). Standard

I/O port with internal pull-up.

EXTIN0 — External Trigger Input.

P1.26 — General purpose input/output digital pin (GPIO).

RTCK — Returned Test Clock output. Extra signal added to the JTAG

port. Assists debugger synchronization when processor frequency

varies. Bidirectional pin with internal pull-up.

Note: LOW on RTCK while RESET is LOW enables pins P1[31:26] to

operate as Debug port after reset.

P1.27 — General purpose input/output digital pin (GPIO).

TDO — Test Data out for JTAG interface.

P1.28 — General purpose input/output digital pin (GPIO).

TDI — Test Data in for JTAG interface.

P1.29 — General purpose input/output digital pin (GPIO).

TCK — Test Clock for JTAG interface. This clock must be slower than

16 of the CPU clock (CCLK) for the JTAG interface to operate.

P1.30 — General purpose input/output digital pin (GPIO).

TMS — Test Mode Select for JTAG interface.

P1.31 — General purpose input/output digital pin (GPIO).

TRST — Test Reset for JTAG interface.

USB bidirectional D+ line.

USB bidirectional D line.

External reset input: A LOW on this pin resets the device, causing

I/O ports and peripherals to take on their default states, and processor

execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator amplifier.

Input to the RTC oscillator circuit.

Output from the RTC oscillator circuit.

Ground: 0 V reference.

Analog ground: 0 V reference. This should nominally be the same

voltage as VSS, but should be isolated to minimize noise and error.

3.3 V power supply: This is the power supply voltage for the core and

I/O ports.

LPC2141_42_44_46_48

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 12 August 2011

© NXP B.V. 2011. All rights reserved.

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