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LPC2141FBD64(2007) Просмотр технического описания (PDF) - NXP Semiconductors.

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LPC2141FBD64 Datasheet PDF : 39 Pages
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NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
Table 3. Pin description …continued
Symbol
Pin
Type
P0.31/UP_LED/ 17[6]
O
CONNECT
O
O
P1.0 to P1.31
I/O
P1.16/
16[6]
I/O
TRACEPKT0
O
P1.17/
12[6]
I/O
TRACEPKT1
O
P1.18/
8[6]
I/O
TRACEPKT2
O
P1.19/
4[6]
I/O
TRACEPKT3
O
P1.20/
48[6]
I/O
TRACESYNC
O
P1.21/
44[6]
I/O
PIPESTAT0
O
P1.22/
40[6]
I/O
PIPESTAT1
O
P1.23/
36[6]
I/O
PIPESTAT2
O
P1.24/
32[6]
I/O
TRACECLK
O
P1.25/EXTIN0 28[6]
I/O
I
P1.26/RTCK 24[6]
I/O
I/O
P1.27/TDO
64[6]
I/O
O
Description
P0.31 — General purpose output only digital pin (GPO)
UP_LED — USB GoodLink LED indicator, it is LOW when device is
configured (non-control endpoints enabled), it is HIGH when the device is not
configured or during global suspend
CONNECT — Signal used to switch an external 1.5 kresistor under the
software control, used with the SoftConnect USB feature
Important: This is an digital output only pin, this pin MUST NOT be externally
pulled LOW when RESET pin is LOW or the JTAG port will be disabled
Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls
for each bit, the operation of port 1 pins depends upon the pin function
selected via the pin connect block, pins 0 through 15 of port 1 are not
available
P1.16 — General purpose input/output digital pin (GPIO)
TRACEPKT0 — Trace Packet, bit 0, standard I/O port with internal pull-up
P1.17 — General purpose input/output digital pin (GPIO)
TRACEPKT1 — Trace Packet, bit 1, standard I/O port with internal pull-up
P1.18 — General purpose input/output digital pin (GPIO)
TRACEPKT2 — Trace Packet, bit 2, standard I/O port with internal pull-up
P1.19 — General purpose input/output digital pin (GPIO)
TRACEPKT3 — Trace Packet, bit 3, standard I/O port with internal pull-up
P1.20 — General purpose input/output digital pin (GPIO)
TRACESYNC — Trace Synchronization, standard I/O port with internal
pull-up
Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to
operate as Trace port after reset
P1.21 — General purpose input/output digital pin (GPIO)
PIPESTAT0 — Pipeline Status, bit 0, standard I/O port with internal pull-up
P1.22 — General purpose input/output digital pin (GPIO)
PIPESTAT1 — Pipeline Status, bit 1, standard I/O port with internal pull-up
P1.23 — General purpose input/output digital pin (GPIO)
PIPESTAT2 — Pipeline Status, bit 2, standard I/O port with internal pull-up
P1.24 — General purpose input/output digital pin (GPIO)
TRACECLK — Trace Clock, standard I/O port with internal pull-up
P1.25 — General purpose input/output digital pin (GPIO)
EXTIN0 — External Trigger Input, standard I/O with internal pull-up
P1.26 — General purpose input/output digital pin (GPIO)
RTCK — Returned Test Clock output, extra signal added to the JTAG port,
assists debugger synchronization when processor frequency varies,
bidirectional pin with internal pull-up
Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate
as Debug port after reset
P1.27 — General purpose input/output digital pin (GPIO)
TDO — Test Data out for JTAG interface
LPC2141_42_44_46_48_3
Product data sheet
Rev. 03 — 19 October 2007
© NXP B.V. 2007. All rights reserved.
10 of 39

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