PCK2510S Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

производитель

PCK2510S

50-150 MHz 110 SDRAM clock driver

Philips Electronics 

Philips Semiconductors

50–150 MHz 1:10 SDRAM clock driver

Product specification

PCK2510S

PIN DESCRIPTIONS

PIN NUMBER SYMBOL

1

AGND

2, 10, 14, 22

VCC

3, 4, 5, 8, 9,

15, 16, 17, 20, 21

1Y (0–9)

6, 7, 18, 19

GND

11

G

12

FBOUT

13

FBIN

23

AVCC

24

CLK

TYPE

GND

PWR

OUT

GND

IN

OUT

IN

PWR

IN

NAME, FUNCTION, and DIRECTION

Analog ground. AGND provides the ground reference for the analog circuitry.

Power supply

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y (0–9) is enabled

via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control

input. Each output has an integrated 25 Ω series-damping resistor.

Ground

Output bank enable. G is the output enable for outputs 1Y (0–9). When G is LOW, outputs 1Y

(0–9) are disabled to a logic LOW state. When G is HIGH, all outputs 1Y (0–9) are enabled and

switch at the same frequency as CLK.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency

as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.

FBOUT has an integrated 25 Ω series-damping resistor.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be

hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so

that there is nominally zero phase error between CLK and FBIN.

Analog power supply. AVCC provides the power reference for the analog circuitry. In addition,

AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL

is bypassed and CLK is buffered directly to the device outputs.

Clock input. CLK provides the clock signal to be distributed by the PCK2510S clock driver. CLK

is used to provide the reference signal to the integrated PLL that generates the clock output

signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock.

Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required

for the PLL to phase lock the feedback signal to its reference signal.

FUNCTION TABLE

INPUTS

G

CLK

X

L

L

H

H

H

OUTPUTS

1Y (0–9)

FBOUT

L

L

L

H

H

H

1999 Dec 13

3

Share Link: