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LMA1010

16 x 16-bit Multiplier-Accumulator

LOGIC Devices 

DEVICES INCORPORATED

DEVICES INCORPORATED

LMA1010/2010

16 x 16-LbiMt MAult1ip0lie1r-A0c/c2um0u1la0tor

16 x 16-bit Multiplier-Accumulator

FEATURES

DESCRIPTION

u 20 ns Multiply-Accumulate Time

u Replaces Fairchild TMC2210,

Cypress CY7C510, IDT 7210L,

and AMD Am29510

u Two’s Complement or Unsigned

Operands

u Accumulator Performs Preload,

Accumulate, and Subtract

u Three-State Outputs

u 68-pin PLCC, J-Lead

LMA1010/2010 BLOCK DIAGRAM

CLK A

CLK B

The LMA1010 and LMA2010 are

high-speed, low power 16-bit

multiplier-accumulators. The LMA1010

and LMA2010 are functionally identical;

they differ only in packaging. Full mili-

tary ambient temperature range opera-

tion is achieved with advanced CMOS

technology.

The LMA1010 and LMA2010 produce

the 32-bit product of two 16-bit numbers.

The results of a series of multiplications

may be accumulated to form the sum of

products. Accumulation is performed to

35-bit precision with the multiplier prod-

uct sign extended as appropriate.

Data present at the A and B input regis-

ters is latched on the rising edges of

CLK A and CLK B respectively. RND,

A15-0

16

A REGISTER

B15-0

R15-0

16

B REGISTER

TC, ACC, and SUB controls are latched

on the rising edge of the logical OR of

CLK A and CLK B. TC specifies the

input as two’s complement

(TC HIGH) or unsigned magnitude

(TC LOW). RND, when HIGH, adds ‘1’

to the most significant bit position of

the least significant half of the product.

Subsequent truncation of the 16 least

significant bits produces a result

correctly rounded to 16-bit preci-

sion.

ACC and SUB control accumulator

operation. ACC HIGH results in

addition of the multiplier product and

the accumulator contents, with the result

stored in the accumulator register on the

rising edge of CLK R. ACC and SUB

HIGH results in subtraction of the

accumulator contents from the

multiplier product, with the result stored

in the accumulator register. With ACC

LOW and SUB LOW, no accumulation

occurs and the next product is loaded

directly into the accumulator register.

ACC LOW and SUB HIGH is undefined.

RND

TC

ACC

SUB

OEX

OEM

OEL

PREL

CLK R

PRELOAD

CONTROL 3

LOGIC

LEX

LEM

LEL

3

OEX

OEM

OEL

LEX

35

32

R

R+A A

R–A

PASS R

35

LEM

LEL

3

16

16

ACCUMULATOR REGISTER

OEX

3

OEM

16

OEL

16

The LMA1010/2010 output register

(accumulator register) is divided into

three independently controlled sec-

tions. The least significant result

(LSR) and most significant result

(MSR) registers are 16 bits in length.

The extended result register (XTR) is

3 bits long. The output signals R15-0

and input signals B15-0 share the same

bidirectional pins.

Each output register has an indepen-

dent output enable control. In addition

to providing three-state control of the

output buffers, when OEX, OEM, or OEL

are HIGH and PREL is HIGH, data can be

preloaded via the bidirectional output

pins into the respective output registers.

Data present on the output pins is

latched on the rising edge of CLK R. The

interrelation of PREL and the enable

controls is summarized in Table 1.

R34-32

R31-16

Multiplier-Accumulators

1

08/16/2000–LDS.10/2010-P

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