LH28F160S5T-L70A Просмотр технического описания (PDF) - Sharp Electronics

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производитель

LH28F160S5T-L70A

Flash Memory 16M (2MB × 8/1MB × 16)

Sharp Electronics 

SHARI=

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Symbol

*o-*20

XJo-DQ,

CE,#,

CE,#

RP#

OE#

WE#

STS

WP#

BYTE#

“PP

“cc

GND

NC

_- -

LHFlGKA9

5

Type

INPUT

INPUT/

OUTPUT

INPUT

INPUT

INPUT

INPUT

OPEN

DRAIN

OUTPUT

INPUT

INPUT

SUPPLY

SUPPLY

SUPPLY

Table 2. Pin Descriptions

Name and Function

ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are

internally latched during a write cycle.

Ao: Byte Select Address. Not used in x16 mode(can be floated).

AI-AK Column Address. Selects 1 of 16 bit lines.

As-At!% Row Address. Selects 1 of 2048 word lines.

A16420 : Block Address.

DATA INPUT/OUTPUTS:

DQo-DC&Inputs data and commands during CUI write cycles; outputs data during memory

array, status register, query, and identifier code read cycles. Data pins float to high-

impedance when the chip is deselected or outputs are disabled. Data is internally latched

during a write cycle.

DQs-DQ15:lnputs data during CUI write cycles in x16 mode; outputs data during memory

array read cycles in xl 6 mode; not used for status register, query and identifier code read

mode. Data pins float to high-impedance when the chip is deselected, outputs are

disabled, or in x8 mode(Byte#=V,, ). Data is internally latched during a write cycle.

CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense

amplifiers. Either CEO# or CE,# VIH deselects the device and reduces power consumption

to standby levels. Both CEn# and CE,# must be VII to select the devices.

RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets

internal automation. RP# VI, enables normal operation. When driven V,,, RP# inhibits

write operations which provides data protection during power transitions. Exit from deep

power-down sets the device to read array mode.

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse.

STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode

(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal

operation (block erase, full chip erase, (multi) word/byte write or block lock-bit

configuration). STS High Z indicates that the WSM is ready for new commands, block

erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is

suspended or the device is in deep power-down mode. For alternate configurations of the

STATUS pin, see the Configuration command.

WRITE PROTECT: Master control for block locking. When VI,, Locked blocks can not be

erased and programmed, and block lock-bits can not be set and reset.

BYTE ENABLE: BYTE# V,, places device in x8 mode. All data is then input or output on

DQO-,, and DQ8-t5 float. BYTE# V,, places the device in x16 mode , and turns off the Ac

input buffer.

BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE. BLOCK LOCK-

BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or

configuring block lock-bits. With Vpp<V+pLK, memory contents cannot be altered. Block

erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid

Vpp (see DC Characteristics) produce spurious results and should not be attempted.

DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do

notfloat any power pins. With VCCIVLKO, all write attempts to the flash memory are

inhibited. Device operations at invalid Vcc voltage (see DC Characteristics) produce

spurious results and should not be attempted.

GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internal connected; it may be driven or floated.

Rev. 1.9

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