LH28F160S5T-L70A Просмотр технического описания (PDF) - Sharp Electronics

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LH28F160S5T-L70A

Flash Memory 16M (2MB × 8/1MB × 16)

Sharp Electronics 

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1 INTRODUCTION

This datasheet contains LH28F160S5T-L70A

specifications. Section 1 provides a flash memory

overview. Sections 2, 3, 4, and 5 describe the

memory organization and functionality. Section 6

covers electrical specifications.

1.1 Product Overview

execute code from any other flash memory arrayI

location.

Individual block locking uses a combination of bit:

and WP#, Thirty-two block lock-bits, to lock ant

unlock blocks. Block lock-bits gate block erase, ful

chip erase and (multi) word/byte write operations

Block lock-bit configuration operations (Set BlocE

Lock-Bit and Clear Block Lock-Bits commands) se

and cleared block lock-bits.

The LH28F160S&T-L70A is a high-performance 16M-

bit Smart 5 Flash memory organized as

2MBx8/1 MBxl6. The 2MB of data is arranged in

thirty-two 64K-byte blocks which are individually

erasable, lockable, and unlockable in-system. The

memory map is shown in Figure 3.

i

Smart 5 technology provides a choice of V,, and

V,, combinations, as shown in Table 1, to meet

system performance and power expectations. 5V V,,

provides the highest read performance. V,, at 5V

eliminates the need for a separate 12V converter,

while V,,=5V maximizes erase and write

performance. In addition to flexible erase and

program voltages, the dedicated V,, pin gives

complete data protection when V,+V,,Lk.

Table 1. Vcc.and VP, Voltage Combinations

Offered by Smart 5 Technology

Vcr: Voltage

Vpp Voltage

5v

I

5v

,

The status register indicates when the WSM’s block

erase, full chip erase, (multi) word/byte write or block

lock-bit configuration operation is finished.

The STS output gives an additional indicator of WSM

activity by providing both a hardware signal of status

(versus software polling) and status masking

(interrupt masking for background block erase, for

example). Status polling using STS minimizes both

CPU overhead and system power consumption. STS

pin can be configured to different states using the

Configuration command. The STS pin defaults tc

RY/BY# operation. When low, STS indicates that the

WSM is performing a block erase, full chip erase,

(multi) word/byte write or block lock-bit configuration.

STS-High Z indicates that the WSM is ready for a

new command, block erase is suspended and (multi)

word/byte write are inactive, (multi) word/byte write

are suspended, or the device is in deep power-down

mode. The other 3 alternate configurations are all

pulse mode for use as a system interrupt.

Internal VCC. and VW detection Circuitry

automatically configures the device for optimized

read and writeoperations.

A Command User Interface (CUI) serves as the

interface between the system processor and internal

operation of the device. A valid command sequence

written to the CUI initiates device automation. An

internal Write State Machine (WSM) automatically

executes the algorithms and timings necessary for

block erase, full chip erase, (multi) word/byte write

and block lock-bit configuration operations.

A block erase operation erases one of the device’s

64K-byte blocks typically within 0.34s (5V Voo, 5V

V,,) independent of other blocks. Each block can be

independently erased 100,000 times (3.2 million

block erases per device). Block erase suspend mode

allows system software to suspend block erase to

read or write data from any other block.

The access time is 70ns (tAvQv) over the commercial

temperature range (0% to +7O”C) and Vc, supply

voltage range of 4.75V-5.25V. At lower Voc voltage,

the access time is 80ns (45V-55V).

The Automatic Power Savings (APS) feature

substantially reduces active current when the device

is in static mode (addresses not switching). In APS

m-ode, the typical lCCR current is 1 mA at 5V V,,.

When either CE,# or CE,#, and RP# pins are at Vcc,

the I,, CMOS standby mode is enabled. When the

RP# pin is at GND, deep power-down mode is

enabled which minimizes power consumption and

provides write protection during reset. A reset time

(tPHav) is required from RP# switching high until

outputs are valid. Likewise, the device has a wake

time (tpHEL) from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset and

the status register is cleared.

A word/byte write is performed in byte increments

typically within 9.24us (5V Vcc, 5V Vpp). A multi

word/byte write has high speed write performance of

2uslbyte (5V Vcc, 5V V,,). (Multi) Word/byte write

suspend mode enables the system to read data or

The device is available in 56-Lead TSOP (Thin Small

Outline Package, 1.2 mm thick). Pinout is shown in

Figure 2.

Rev. 1.9

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