LD39150XX12 Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге

Компоненты Описание

производитель

LD39150XX12

Ultra low drop BiCMOS voltage regulator

STMicroelectronics 

Pin configuration

2

Pin configuration

LD39150xx

Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN)

DFN6 (3x3 mm)

PPAK

DPAK

Table 2. Pin description

Pin n°

DFN PPAK DPAK

SYMBOL

NOTE

5

5

VSENSE/N.C.

For fixed versions: to be connected with LDO output voltage pins for DFN

package and not connected on PPAK

ADJ

For adjustable version: Error amplifier input pin for VO from 1.22 to 5.0 V

3

2

1

VI

LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a

distance of not more than 0.5’’ from input pin.

4

4

3

2

1

VO

VINH

LDO output voltage pins, with minimum CO = 2.2 µF needed for stability

(also refer to CO vs ESR stability chart)

Inhibit input voltage: ON MODE when VINH ≥ 2 V, OFF MODE when VINH ≤

0.3 V (Do not leave floating, not internally pulled down/up)

1

3

2

GND Common ground

6

N.C. Not connected

4/19

Share Link: