LC7986 Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC7986

LCD Controller/Driver

SANYO -> Panasonic 

LC7986C

Functional Description

Registers

The LC7986C has two 8-bit registers—instruction register

(IR) and data register (DR)—that are selected as shown in

the following table.

RS R/W

Operation

0 0 IR write, instruction execution

0 1 Busy flag (DB7) and address counter (DB0 to DB6) output

1 0 DR write, internal DR to DD RAM or CG RAM data transfer

1 1 DR read, internal DD RAM or CG RAM to DR data transfer

The instruction register is write-only. It contains instruc-

tion codes or DD RAM and CG RAM addresses written

by the microcontroller.

The data register holds data read from or written to either

DD RAM or CG RAM. Data written to the data register by

the microcontroller is automatically transferred to the cur-

rent DD RAM or CG RAM address. Data read from

DD RAM or CG RAM is buffered in the data register.

When the microcontroller writes a DD RAM or CG RAM

address to the instruction register, the data at that address

is copied into the data register. The microcontroller then

reads the data in the data register to complete the transfer.

Once that data is read, the data from the next DD RAM or

CG RAM address is copied into the data register in prepa-

ration for the next data read.

Busy Flag

When busy flag is 1, the previous instruction is executing,

and when 0, the instruction has completed. The next

instruction cannot be received until BF is 0. The microcon-

troller should, therefore, confirm that BF is 0 before writ-

ing the next instruction.

Address Counter

The address counter is used for both the DD RAM and the

CG RAM. The address output on DB0 to DB7 is the

counter value before the currently executing instruction

began.

Display Data RAM (DD RAM)

The display data RAM stores 80, 8-bit character codes, and the LC7986C can display a maximum of 80 characters. The

address counter contains the location for the next display memory read or write operation as shown in the following fig-

ure.

Display data addresses are in hexadecimal. For example, the address counter contents for location 4E are shown in the

following figure.

To prevent undesirable effects such as display flicker during DD RAM accesses, the internal memory and the micropro-

cessor interface have separate timing signals.

Single-line display mode (N = 0)

The DD RAM addresses and their corresponding display positions for an 80-character display are shown in the following

figure.

No. 4101—9/32

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