DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

LC78622NE Просмотр технического описания (PDF) - SANYO -> Panasonic

Номер в каталоге
Компоненты Описание
производитель
LC78622NE
SANYO
SANYO -> Panasonic SANYO
LC78622NE Datasheet PDF : 31 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC78622NE
Pin Functions
Pin No. Symbol
I/O
Function
Output pin states
during a reset
1
DEFI
I Defect detection signal (DEF) input. (Must be connected to 0 V when unused.)
2
TAI
I
Test input. A pull-down resistor is built in. Must be connected to 0 V.
3
PDO
O
Internal VCO control phase comparator output
4
VVSS
PLL pins
Internal VCO ground. Must be connected to 0 V.
5
ISET
AI
PDO output current adjustment resistor connection
6
VVDD
Internal VCO power supply
7
FR
AI
VCO frequency range adjustment
8
VSS
– Digital system ground. Must be connected to 0 V.
9
EFMO
O
Slice level control
10
EFMIN
I
EFM signal output
EFM signal input
Undefined
11
TEST2
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
12
CLV+
O Disc motor control output.
13
CLV
O Three-value output is also possible when specified by microprocessor command.
Low-level output
Low-level output
Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and
14
V/P
O a low level during phase control.
Low-level output
15
HFL
I Track detection signal input. This is a Schmitt input.
16
TES
I Tracking error signal input. This is a Schmitt input.
17
TOFF
O Tracking off output
High-level output
18
TGL
O Tracking gain switching output. Increase the gain when low.
Undefined
19
JP+
O Track jump output.
20
JP
O Three-value output is also possible when specified by microprocessor command.
Low-level output
Low-level output
21
PCK
O EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.
Low-level output
Synchronization signal detection output. Outputs a high level when the synchronization signal detected from
22
FSEQ
O the EFM signal and the internally generated synchronization signal agree.
Undefined
23
VDD
– Digital system power supply.
24
CONT1
I/O General-purpose I/O pin 1
Input
25
CONT2
I/O General-purpose I/O pin 2 Controlled by serial data commands from the microprocessor. Any of these
26
CONT3
I/O General-purpose I/O pin 3 that are unused must be either set up as input ports and connected to 0 V,
27
CONT4
I/O General-purpose I/O pin 4 output ports and set up as left open.
Input
Input
Input
28
CONT5
I/O General-purpose I/O pin 5
Input
29 EMPH/CONT6 O De-emphasis monitor pin. A high level indicates playback of a emphasis disk./general-purpose I/O port 6 Low-level output
30
C2F
O C2 flag output
Undefined
31
DOUT
O Digital output. (EIAJ format)
Undefined
32
TEST3
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
33
TEST4
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
General-purpose I/O command identification pin. A pull-down resistor is built in.
If only the same functions as those provided by the LC78622E are used, this pin must be left open or
34
PCCL
I connected to 0 V.
High: Only the general-purpose I/O port commands are allowed.
Low: All commands are allowed.
35 MUTEL/CONT7 O
Left channel mute output/general-purpose I/O port 7
High-level output
36
LVDD
Left channel
Left channel power supply
37
LCHO
O one-bit D/A converter
Left channel output
38
LVSS
39
RVSS
40
RCHO
O Right channel
41
RVDD
– one-bit D/A converter
42 MUTER/CONT8 O
Left channel ground. Must be connected to 0 V.
Right channel ground. Must be connected to 0 V.
Right channel output
Right channel power supply
Right channel mute output/general-purpose I/O port 8
High-level output
43
XVDD
– Crystal oscillator power supply.
44
XOUT
O
Connections for a 16.9344 MHz crystal oscillator element
45
XIN
I
46
XVSS
– Crystal oscillator ground. Must be connected to 0 V.
47
SBSY
O Subcode block synchronization signal output
Undefined
48
EFLG
O C1, C2, single and double error correction monitor pin
Undefined
49
PW
O Subcode P, Q, R, S, T, U, V and W output
Undefined
50
SFSY
O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. Undefined
Continued on next page.
No. 6015-7/31

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]