LC78630 Просмотр технического описания (PDF) - SANYO -> Panasonic
Номер в каталоге
Компоненты Описание
производитель
LC78630 Datasheet PDF : 33 Pages
| |||
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Symbol
VPDO
PDO2
PDO1
AVSS
FR
AVDD
ISET
TAI
EFMO
VSS
EFMI
TEST1
CLV+
CLV–
V/P
TEST2
TEST3
P4
HFL
TES
PCK
22
FSEQ
23
TOFF
24
TGL
25
THLD
26
TEST4
27
VDD
28
JP+
29
JP–
30
SLD+
31
SLD–
32
EMPH
33
P5
34
LRCKO
35
DFLRO
36
DACKO
37
CONT1
38
P0/DFCK
39
P1/DFIN
40
P2
41
P3/DFLR
42
LRSY
43
CK2
44
ROMXA
45
C2F
46
MUTEL
47
LVDD
48
LCHP
49
LCHN
50
LVSS
LC78630E
I/O
Function
O Variable pitch PLL charge pump output. Must be left open if unused.
O Double-speed and quad-speed mode playback PLL charge pump output. Must be left open if unused.
O Normal-speed mode playback PLL charge pump output
Analog system ground. Normally 0 V.
Built-in VCO frequency range setting resistor connection
Analog system power supply.
PDO1 and PDO2 output current setting resistor connection
I
Test input. A pull-down resistor is built in.
O EFM signal output
Digital system ground. Normally 0 V.
I
EFM signal input
I
Test input. A pull-down resistor is built in.
O
Spindle servo control output. CLV+ outputs a high level for acceleration, and CLV– outputs a high level for
O deceleration.
Rough servo/phase control automatic switching monitor output. A high-level output indicates rough servo, and a
O
low-level output indicates phase control.
I
Test input. A pull-down resistor is built in.
I
Test input. A pull-down resistor is built in.
I/O I/O port
I
Track detection signal input. This is a Schmitt input.
I
Tracking error signal input. This is a Schmitt input.
O
EFM data playback bit clock monitor. Outputs 4.3218 MHz when the phase is locked in normal-speed mode
playback.
Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the
O
EFM signal matches the internally generated synchronization signal.
O Tracking off output
O Tracking gain switching output. Increase the gain when this pin outputs a low level.
O Tracking hold output.
I
Test input. A pull-down resistor is built in.
Digital system power supply.
O
Track jump output. JP+ outputs a high level both for acceleration during outward direction jumps and for
deceleration during inward direction jumps. JP– outputs a high level both for acceleration during inward direction
O jumps and for deceleration during outward direction jumps.
O
Sled output. This pin can be set to 1 of 4 levels by commands sent from the system control microprocessor.
O
O De-emphasis monitor. A high level indicates that a disk requiring de-emphasis is being played.
I/O I/O port
O
LR clock output
O
Digital filter outputs
LR data output. The digital filter can be turned off with the DFOFF command.
O
Bit clock output
O Output port
I/O I/O port or digital filter bit clock input
I/O I/O port or digital filter data input
I/O port. Used as the de-emphasis filter on/off switching pin in antishock mode. The de-emphasis filter is turned
I/O on when this pin is high.
I/O I/O port output or digital filter LR clock input (when anti-shock mode)
O
LR clock output
O
ROMXA pins
O
O
Bit clock output. The polarity can be inverted with the CK2CON command.
Interpolated data output. Data that has not been interpolated can be output by issuing
the ROMXA command.
C2 flag output
O
Left channel mute output
Left channel power supply.
O
One-bit D/A
O
converter pins
Left channel P output
Left channel N output
Left channel ground. Normally 0 V.
No. 5121-8/33
Share Link: 