LC78628E Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC78628E

Compact Disc Player DSP with Built-in HDCD Decoder

SANYO -> Panasonic 

LC78628E

Internal Functions

1. HF signal input circuit — Pin 11: EFMIN, pin 10: EFMO, pin 1: DEFI, pin 13: CLV+

When an HF signal is input to the EFMIN pin, an

10 EFMO

EFM signal (NRZ) sliced at the optimal level is

acquired. As a measure to handle defects, when the

SLC

SLI

DEFI pin (pin 1) goes high, the slice level

controller output from the EFMO pin (pin 10) goes

to the high-impedance state, and the slice level is

held. However, this is only valid when the CLV

VREF

circuit is in phase control mode, that is, when the

HF signal

11 EFMIN

V/P pin (pin 15) is outputting a low level.

This function can be implemented in combination

with the DEF pin from an LA9230/9240 series

A12803 product.

*: If the EFMIN and CLV+ lines are run close

together, the error rate may increase due to

spurious radiation. We recommend inserting

either a ground or VDD shield line between these

lines.

2. PLL clock regeneration circuit — Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK

VDD

Frequency

and phase

comparator

EFM(NRZ)

R1

5 ISET

Charge pump

C1

3 PDO

R2

7 FR

C2

VCO

1/N

R3

21 PCK

The LC78628E includes a built-in VCO circuit,

and a PLL circuit is formed by adding external

resistors and capacitors. The ISET pin sets the

charge pump reference current, PDO sets the VCO

circuit loop filter, and FR sets the VCO frequency

range.

Sample values for reference purposes:

R1 = 68 kΩ, C1 = 0.1 µF

R2 = 680 Ω, C2 = 0.1 µF

R3 = 1.2 kΩ

A12804

Code

Command

Frequency divisor

RES = low

$AC

VCO × 2 SET

$AD

VCO × 1 SET

$AE

VCO × 0.5 SET

1

2

0.5

q

The divisor used by the divider to create PCK from the VCO can be set using the VCO × 2, VCO × 1, and VCO × 0.5 SET instructions. Normally, the circuit

operates in the VCO × 0.5 SET state after a reset.

No. 6329-11/40

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