LC78626KE Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC78626KE Datasheet PDF : 34 Pages
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LC78626KE
Continued from preceding page.
Pin
Pin
No.
Name
I/O
Description
Output pin states
during reset
General I/O pin 3. This controls the commands from the microcontroller. This pin is shared exclusively with
34 CONT3/SBCK I/O the subcode read clock input (SBCK). When not used, either set this as an input port and connect to 0 V, or Input mode
set this as an output port and leave it open.
General I/O pin 4. This controls the commands from the microcontroller. This pin is shared exclusively with
35 CONT4/SFSY I/O the subcode frame sync signal output (SFSY). When not used, either set this as an input port and connect Input mode
to 0 V, or set this as an output port and leave it open.
General I/O pin 5. This controls the commands from the microcontroller. This pin is shared, exclusively, with
36 CONT5/PW I/O the subcode P, Q, R, S, T, U, V, W output (PW). When not used, either set this as an input port and connect Input mode
to 0 V, or set this as an output port and leave it open.
37 SBSY
O Subcode block sync signal output
Undefined
38 TEST3
I Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
—
39 DOUT
O Digital output. EIAJ format.
Undefined
40 TEST4
I Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
—
41
16M/NGJ
O Shared function pin that functions either as the 16.9344 MHz output (16M) or as the C2 flag data continuity check Clock output
start signal (detection start is indicated by a low to high transition). Controlled by microcontroller commands.
42 4.2M
O 4.2336 MHz output
43 EFLG
O C1, C2, one error, two error error correction monitor output
44 FSX
O 7.35 kHz sync signal output (frequency divided from the crystal oscillator).
45 EMPH
O Deemphasis monitor output. When high level, a deemphasis disk is being played back.
46 C2F
O C2 flag output
47 TOUT
O Test output. Under normal operation, this should be left open.
48 MR1
49 MR2
I DRAM switch: high : 1M, low : 4M
I 1 M: high, low 4 M: low, low 16 M: low, high 4 M X 2: high, high (MR1, MR2)
50 TESD
I Test input. Must be connected to 0V.
51 MUTESL
O
L channel mute output
52 LVDD
53 LCHO
54 L/RVSS
55 RCHO
P
L channel power supply
AO
L channel output
P For the one-bit D/A L/R channel ground. Must be connected to 0 V.
AO converter
R channel output
56 RVDD
P
57 MUTER
O
R channel power supply
R channel mute output
58 XVDD
59 XOUT
60 XIN
P Crystal oscillator power supply
O
16.9344 MHz crystal oscillator connection
I
61 XVSS
62 RWC
P Crystal oscillator ground. Must be connected to 0 V.
I Read/write control input. Schmidt input.
63 COIN
I Microcontroller command input
64 CQCK
I Input pin for the command input latch clock and the subcode readout clock. Schmitt input.
65 SQOUT
O Subcode Q output
66 WRQ
O Subcode Q output standby output
67 FMT
I Operating mode switch: high: shock proof, low: through.
68 EMPP
O DRAM empty (an RZP pulse is output when the DRAM is empty).
69 RES
I External reset input: low reset (all internal blocks are reinitialized).
Clock output
Undefined
Undefined
Low-level output
Undefined
Undefined
—
—
High-level output
—
—
—
—
—
High-level output
—
—
—
—
—
—
Undefined
Undefined
—
Low-level output
—
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No. 5995-9/34
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