LC78625 Просмотр технического описания (PDF) - SANYO -> Panasonic
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производитель
LC78625 Datasheet PDF : 35 Pages
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LC78625E
Continued from preceding page.
Pin No. Symbol I/O
Function
38 ASDACK/P0 I/O • When antishock mode is not used,
39 ASDFIN/P1 I/O these pins are used as general-
purpose I/O ports (P0 to P3). They
The antishock inputs in
40 ASDEPC/P2 I/O must either be set to input mode and antishock mode.
connected to 0 V, or set to output
41 ASLRCK/P3 I/O mode and left open, if unused.
Bit clock input
Left and right channel data input
Sets the built-in de-emphasis filter on or off.
(High: on, low: off)
L/R clock input
42
LRSY
O
L/R clock output
43
CK2
O
ROMXA application output signals
44
ROMXA
O
Bit clock output
(after reset)
Interpolation data output
(after reset)
Inverted polarity clock output
(during CK2CON mode)
ROM data output (during ROMXA mode)
45
C2F
O
C2 flag output
46
MUTEL
O
Left channel mute output
47
LVDD
48
LCHP
O
Left channel power supply
Left channel P output
49
LCHN
O
Left channel N output
50
LVSS
51
RVSS
One-bit D/A converter signals
52
RCHN
O
Left channel ground. Must be connected to 0 V.
Right channel ground. Must be connected to 0 V.
Right channel N output
53
RCHP
O
Right channel P output
54
RVDD
55
MUTER
O
Right channel power supply
Right channel mute output
56
DOUT
O Digital output
57
SBSY
O Subcode block synchronization signal output
58
EFLG
O C1, C2, single and double error correction monitor pin
59
PW
O Subcode P, Q, R, S, T, U and W output
60
SFSY
O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state.
61
SBCK
I Subcode readout clock input. This is a Schmitt input. (This pin must be connected to 0 V if unused.)
62
FSX
O Output for the 7.35 kHz synchronization signal divided from the crystal oscillator
63
WRQ
O Subcode Q output standby output
64
RWC
I Read/write control input. This is a Schmitt input.
65
SQOUT
O Subcode Q output
66
COIN
I Command input from the control microprocessor
67
CQCK
I Input for the command input acquisition clock or the SQOUT pin subcode readout clock input. This is a Schmitt input.
68
RES
I Reset input. This pin must be set low briefly after power is first applied.
69
TST11
O Test output. Leave open. (Normally outputs a low level.)
70
LASER
O Laser on/off output. Controlled by serial data commands from the control microprocessor.
71
16M
O 16.9344 MHz output
72
4.2M
O 4.2336 MHz output
73
CONT
O Supplementary control output. Controlled by serial data commands from the control microprocessor.
74
TEST5
I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
75
CS
I Chip select input. A pull-down resistor is built in. This pin must be connected to 0 V if unused.
76
XVSS
Crystal oscillator ground. Must be connected to 0 V.
77
XIN
I
Connections for a 16.9344 MHz crystal oscillator
78
XOUT
O
79
XVDD
Crystal oscillator power supply
80
TEST1
I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
Note: All power-supply pins (VDD, VVDD, LVDD, RVDD, and XVDD) must be connected to the same potential.
No. 5502-9/35
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