LC75816E Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC75816E

1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers with Key Input Function

SANYO -> Panasonic 

LC75816E, 75816W

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter

Maximum supply voltage

Input voltage

Output voltage

Output current

Allowable power dissipation

Operating temperature

Storage temperature

Symbol

VDD max

VLCD max

VIN1

VIN2

VIN3

VOUT1

VOUT2

VOUT3

IOUT1

IOUT2

IOUT3

IOUT4

Pd max

Topr

Tstg

Conditions

VDD

VLCD

CE, CL, DI, INH

OSCI, KI1 to KI5, TEST

VLCD1, VLCD2, VLCD3, VLCD4

DO

OSCO, KS1 to KS6, P1, P2

VLCD0, S1 to S65, COM1 to COM10

S1 to S65

COM1 to COM10

KS1 to KS6

P1, P2

Ta = 85°C

Ratings

Unit

–0.3 to +7.0

V

–0.3 to +11.0

–0.3 to +7.0

–0.3 to VDD + 0.3

V

–0.3 to VLCD + 0.3

–0.3 to +7.0

–0.3 to VDD + 0.3

V

–0.3 to VLCD + 0.3

300

µA

3

1

mA

5

200

mW

–40 to +85

°C

–55 to +125

°C

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Supply voltage

Output voltage

Input voltage

Input high level voltage

Input low level voltage

Recommended external resistance

Recommended external capacitance

Guaranteed oscillation range

Data setup time

Data hold time

CE wait time

CE setup time

CE hold time

High level clock pulse width

VDD

VDD

4.5

6.0

VLCD: When the display contrast adjustment circuit is used.

7.0

VLCD

VLCD: When the display contrast adjustment circuit is not used.

4.5

10.0

V

10.0

VLCD0

VLCD0

VLCD4+4.5

VLCD

V

VLCD1

VLCD1

3/4 (VLCD0–VLCD4) VLCD0

VLCD2

VLCD3

VLCD2

VLCD3

2/4 (VLCD0–VLCD4) VLCD0

V

1/4 (VLCD0–VLCD4) VLCD0

VLCD4

VLCD4

0

1.5

VIH1

CE, CL, DI, INH

0.8 VDD

6.0

VIH2

OSCI

0.7 VDD

VDD

V

VIH3

KI1 to KI5

0.6 VDD

VDD

VIL1

CE, CL, DI, INH, KI1 to KI5

VIL2

OSCI

0

0.2 VDD

V

0

0.3 VDD

ROSC

OSCI, OSCO

33

kΩ

COSC

OSCI, OSCO

220

pF

fOSC

OSC

150

300

600 kHz

tds

CL, DI: Figure 2

160

ns

tdh

CL, DI: Figure 2

160

ns

tcp

CE, CL: Figure 2

160

ns

tcs

CE, CL: Figure 2

160

ns

tch

CE, CL: Figure 2

160

ns

tøH

CL: Figure 2

160

ns

Low level clock pulse width

tøL

CL: Figure 2

160

ns

DO output delay time

DO rise time

tdc

DO, RPU = 4.7kΩ, CL = 10pF*1: Figure 2

tdr

DO, RPU = 4.7kΩ, CL = 10pF*1: Figure 2

1.5

µs

1.5

µs

Note: *1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL.

No. 7142-4/43

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