LC74772V(1997) Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC74772V Datasheet PDF : 16 Pages
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LC74772V
Display Control Commands
The display control commands have an 8-bit serial input format. Data is input LSB first.
Display Control Command Table
Command
COMMAND 0
System setup 1
COMMAND 1
System setup 2
COMMAND 2
Input control setup
COMMAND 3
General-purpose port control
COMMAND 4
Display operation control:
reverse video and blinking
COMMAND 5
Display control: on/off settings
for each output
COMMAND 6
Output control: systems 3 and 4
COMMAND 8
Display control: border
COMMAND 9
Display start position
COMMAND 10
Display line control
COMMAND 11
RAM write address
COMMAND 14
Display RAM setup data
First byte
Second byte
Command code
Data
Data
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
RST RAM OSC TST
0
0
0
0 SYS CLR STP MOD — — — — — — — —
CSYN CLK CLK CLK
0
0
0
1 MOD POLT MOD1 MOD0 — — — — — — — —
VSYN HSYN DATA ART
0
0
1
0 POLT POLT FMT FMT — — — — — — — —
PORT OUT OUT OUT
0
0
1
1 SET P11 P10 P9 — — — — — — — —
0
1
0
0 RVS BLK BLK BLK — — — — — — — —
ON ON 1
0
0
1
0
1 DSP DSP DSP DSP — — — — — — — —
4
3
2
1
DSPF DSP DSP DSP
0
1
1
0 SL34 RSG GSG BSG — — — — — — — —
BKC BKC BKC BKO4 BKO4 BKO3 BKO3 BKO2 BKO2 BKO1 BKO1
1
0
0
0
0
R G B F1 F0 F1 F0 F1 F0 F1 F0
1
0
0
1 VP5 VP4 VP3 VP2 VP1 VP0 HP5 HP4 HP3 HP2 HP1 HP0
LNF LNF LNF LN
LIN LIN LIN LIN LIN LIN
1
0
1
0
SZ OT4 OT3 SEL 0
0 126 115 104 93 82 71
VADR VADR VADR VADR
HADR HADR HADR HADR HADR
1
0
1
1
3
2
1
0
0
0
0
4
3
2
1
0
1
1
1 BLK RV R G
B C7 C6 C5 C4 C3 C2 C1 C0
x
y
x Command code: (These 4 bits in the first byte identify the command.)
Command 14 is recognized by the upper 3 bits.
y Command data: (These bits specify the data for each command.)
• For commands 0 through 7, 8 bits of data are read in.
• For commands 8 through 14, 16 bits of data are read in.
• If the command 1 data-9 bit (DATAFMT) was set to 1, after the first byte of a command 14 is read
in, the system goes to continuous transfer mode for reading in a series of following bytes.
Note: 1. If the CS pin is set high, the command state is set to the command 0 (system control setup) state.
2. If a system reset is executed from the RST pin or by a command reset, the command register is set tot 0.
No. 5159-6/16
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