LC72714W Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC72714W

Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder

SANYO -> Panasonic 

Continued from preceding page.

Pin No.

Pin

LC72714W

Function

56

CIN

Subcarrier input (comparator input)

I/O

Input

52

VREF

Reference voltage output (Vdda/2)

Output

Pin circuit

+

–

Vref

Vdda

Vssa

36

DO

CCB serial interface data output

Output

37

50

NC

This pin must be left open

57

54

VDDA

Analog system power supply

—

51

VSSA

Analog system ground

—

2, 15, 34

VDDD

Digital system power supply (+2.7 V to +3.6 V)

—

14, 35, 63

VSSD

Digital system ground

—

Notes: 1. This pin must be connected to VDDD or VSSD if the IC is used in serial interface mode (when SP is high).

2. A capacitor of at least 2000 pF must be inserted between VDDD and VSSD.

3. When used in the SP = high mode (as set by the serial interface), the D0 to D7 data bus lines must be connected to either VDDD or VSSD.

Control Registers

This IC includes both registers that can be read and registers that can be written. These registers can be accessed using

either the serial interface (CCB) or the parallel interface. The SP pin switches between these interfaces.

The initial values of the write registers are the data loaded into internal registers when a reset signal (RST) is received.

These values are recommended values that do not need to be changed during normal operation.

If the parallel interface is used, applications must hold the address fixed at 00H when reading out data to which error

correction has been applied. If the CCB interface is used, the application needs only to specify the CCB address (#FB).

The address 00H is an invalid address for writing.

The addresses other than those specified below are control addresses particular to the IC. Applications must not specify

those addresses.

Address Register

Function

R/W Address Register

Function

R/W

1

BIC Number of allowable BIC errors

W

1

STAT Status register

R

2

SYNCB Block synchronization: error protection count

W

2

BLNO Block number register

R

3

SYNCF Frame synchronization: error protection count W

4

CTL1 Control register 1

W

5

CTL2 Control register 2

W

6

CRC4 Layer 4 CRC register

W

No. 6871-6/29

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