LC72338 Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC72338

Single-Chip Microcontrollers with Built-In LCD Driver and PLL Circuits

SANYO -> Panasonic 

LC72336, 72338

Continued from preceding page.

Pin No.

Symbol

I/O

I/O type

64

PJ0/DAC0

63

62

PJ1/DAC1

PJ2/DAC2

O

N-channel open

drain

61

PJ3/DAC3

Function

Shared-function general-purpose and D/A converter output port

The IOS instruction (Pn = 9) is used to switch these pins between the general-purpose

and D/A converter output port functions.

Since these pins are open drain circuits, pull-up resistors are required in external circuits

accepting these outputs.

• When used as a general-purpose port:

Set the general-purpose input port function with the IOS instruction (Pn = 9).

• When used for D/A converter output:

Use the IOS instruction (Pn = 9) to switch the port in bit units.

D/A converter data is loaded into the DAC0 to DAC3 specified with the DAC instruction.

Although a PWM waveform is output as soon as the port is switched, after data is

loaded, the data prior to that load is output for up to 114 µs (1/8.79 kHz).

In clock stop mode, these outputs go to the transistor off (high output) state.

The general-purpose output port function is selected after a power-on reset, and the

outputs go to the transistor off (high output) state.

Shared-function general-purpose I/O and external interrupt port

There is no instruction that switches between the general-purpose port and the external

interrupt pin functions. Rather, the corresponding pin becomes an input-only pin (output

disabled) at the point where the external interrupt enable flag for that pin is set.

• When used as a general-purpose I/O port:

22

PK0/INT0

Input or output can be specified in bit units (bit I/O).

The IOS instruction is used to specify input or output in bit units.

21

PK1/INT1

• When used as external interrupt pins:

20

PK2

I/O CMOS push-pull

These pins are enabled by setting the external interrupt enable flags (INT0EN and

INT1EN) in status register 2. At that point the pin is automatically set up to be an input

19

PK3

port.

The status register 1 interrupt enable flag (INTEN) must also be set to enable interrupt

operation.

Use the IOS instruction (Pn = 3, b1 = INT1, b0 = INT0) to select rising or falling edge

detection.

Input is disabled with the pins in the high-impedance state in clock stop mode.

The general-purpose input port function is selected after a power-on reset.

60

59

79

2

58

57

56

55 to 40

Vdd1

Vdd2

TEST1

TEST2

COM1

COM2

COM3

S1 to S16

—

—

—

O

CMOS 3-value

output

O

CMOS 3-value

output

Apply the LCD drive bias 2/3 voltage to this pin.

Apply the LCD drive bias 1/3 voltage to this pin.

LSI test pin

This pin must be left open or connected to ground.

LCD driver common output pins

This drive circuit implements a 1/3-duty, 1/3-bias drive scheme.

These pins are fixed at the low level in clock stop mode.

These pins are fixed at the low level after a power-on reset.

LCD driver segment output pins

This drive circuit implements a 1/3-duty, 1/3-bias drive scheme.

The frame frequency is 100 Hz.

These pins are fixed at the low level in clock stop mode.

These pins are fixed at the low level after a power-on reset.

Continued on next page.

No. 5157-10/16

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