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LC6513A(2001) Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC6513A Datasheet PDF : 24 Pages
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LC6512A, LC6513A
Appendix 2. lnternal Architecture of LC6512A, 6513A
The LC6512A, 6513A are identical with the LC6502C, 6505C in the internal architecture and instruction set except that
output ports are of high-voltage type and port A is of low-threshold input type and the standby function is the same as for
the LC6514B. For details, refer to ''LC6500 SERIES USER'S MANUAL''; and for the standby function, refer to Appendix
4 ''Standby Function''.
2-1. PC
For the LC6512A, 6513A, this is organized with an 11-bit, 10-bit binary counter, respectively, which specifies the
ROM address of an instruction to be executed next. The high-order 3(2) bits specify a page and the low-order 8 bits
specify an address in the page. The page is updated automatically. ( ) is for the LC6513A.
2-2. ROM
This is used to store user programs. For the LC6512A, 6513A,this is organized with 2048x 8 bits, 1024 x 8 bits,
respectively. By using the ROM table read instruction, the whole area can be accessed and the display pattern can be
programmed.
2-3. Stack
This is used to save the contents of the PC at the subroutine call or interrupt mode. This allows subroutine nesting up
to 8 levels.
2-4. DP
This is a register organized with 4-bit DPL and 3-bit, 2-bit DPH for the LC6512A, 6513A, respectively. When access-
ing the data RAM, the DPL, DPH specify a column address, row address, respectively. When accessing input/output
ports, the DPL specifies port A to port l. The DPL also specifies internal pseudo port O.
2-5. RAM
This is a static RAM used to store data. For the LC6512A, 6513A, this is organized with 128 x 4 bits, 64 x 4 bits,
respectively. Row address 7H(3H) is allocated for 16 flags and 8 working registers which can be manipulated without
being addressed by the DP. ( ) is for the LC6513A.
2-6. AC, E
The AC is a 4-bit register which stores data to be processed by instructions. The E register is an auxiliary register to be
back up the AC and is used as a temporary register or general-purpose register at the instruction execution mode.
2-7. ALU
This is a circuit which performs arithmetic and logic operations specified by individual instructions. This outputs not
only data of operation results but also the status of carry (C), zero (Z).
2-8. Status register
This is a 4-bit register which stores the status of carry, zero and the external interrupt, timer interrupt request.
The contents of the status register can be tested by the branch instructions.
2-9. Timer
This consists of a 4-bit fixed prescaler and an 8-bit programmable timer. This counts the system clock and requests a
timer interrupt when an overflow occurs.
2-10. Control register
This is a 4-bit register, 2-bits of which control input/output of input/output common ports C, D and 2-bits of which
enable/disable external interrupt, internal timer interrupt.
2-1 1. Input/output ports
There are 9 ports/34 pins from port A to I. Each port is addressed by the DPL. Ports A, B are of normal-voltage input
type, ports C, D are of normal-voltage input/output common type, and ports E, F, G, H, I contain FLT drivers. Port A
is of low-threshold input type.
No.236710/24

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