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LB11872V Просмотр технического описания (PDF) - SANYO -> Panasonic

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LB11872V Datasheet PDF : 12 Pages
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LB11872V
Continued from preceding page.
Pin No.
Symbol
Pin Description
29
MN
Monitor pin.
This pin should be left open in normal operation.
31
CSD
Used for both initial reset pulse generation and as the
reference time for constraint protection circuits.
Insert a capacitor between this pin and ground.
VREG
Equivalent Circuit
300
12
32
FG
FG pulse output.
This is an open-collector output.
VREG
14
33
S/S
Start/stop control.
Low: Start 0V to 1.0V
High: Stop 2.0V to VREG
This pin goes to the high level when open.
VREG
34
CLK
Clock input.
Low: 0V to 1.0V
High: 2.0V to VREG
This pin goes to the high level when open.
VREG
35
LD
Phase locked state detection output.
This output goes to the on state when the PLL locked
state is detected.
This is an open-collector output.
VREG
5k
15
5k
16
17
Continued on next page.
No.A0367-8/12

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