L9825TR Просмотр технического описания (PDF) - STMicroelectronics
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L9825TR Datasheet PDF : 11 Pages
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L9825
ELECTRICAL CHARACTERISTCS (continued)
(4.5V ≤ VCC ≤ 5.5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Diagnostics
VDG Diagnostic threshold voltage
0.32·VCC
IOL Open load detection sink current Vout = VDG
20
tdf Diagnostic detection filter time for
15
output 1 & 2 on each diagnostic
condition
Outputs timing
tdon1 Turn ON delay of OUT 1 and 2
NON1, 2 = 50% to VOUT = 0.9·Vbat
NCS = 50% to VOUT = 0.9·Vbat
tdon2 Turn ON delay of OUT 3 to 8
NCS = 50% to VOUT = 0.9·Vbat
tdoff Turn OFF delay of OUT 1 to 8
NCS = 50% to VOUT = 0.1·Vbat
NON1, 2 = 50% to VOUT = 0.1·Vbat
dUon1/dt Turn ON voltage slew-rate
For output 3 to 8; 90% to 30% of 0.7
Vbat; RL = 500Ω; Vbat = 16V
dUon2/dt Turn ON voltage slew-rate
For output 1 and 2; 90% to 30%
2
of Vbat; RL = 500Ω; Vbat = 16V
dUoff1/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 90% of
2
Vbat; RL = 500Ω; Vbat = 16V
dUoff2/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 80% of
2
Vbat; RL = 500Ω; Vbat = 0.9 · Vclp
Serial diagnostic link (Load capacitor at SDO = 100pF)
fclk Clock frequency
50% duty cycle
3
tclh Minimum time CLK = HIGH
160
tcll Minimum time CLK = LOW
160
tpcld Propagation delay
CLK to data at SDO valid
4.9V ≤ VCC ≤ 5.1V
tcsdv
NCS = LOW to data at SDO
active
tsclch CLK low before NCS low
Setup time CLK to NCS change H/L 100
thclcl CLK change L/H after NCS = low
100
tscld SDI input setup time
CLK change H/L after SDI data
20
valid
thcld SDI input hold time
SDI data hold after CLK change H/L
tsclcl CLK low before NCS high
150
thclch CLK high after NCS high
150
tpchdz NCS L/H to output data float
NCS pulse filter time
Multiple of 8 CLK cycles
Typ.
Max.
0.4·VCC
100
50
5
10
10
3.5
10
10
15
100
100
20
100
Unit
V
µA
µs
µs
µs
µs
V/µs
V/µs
V/µs
V/µs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5/11
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