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L6919C

5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT

STMicroelectronics 

L6919C

DIGITAL TO ANALOG CONVERTER

The built-in digital to analog converter allows the adjustment of the output voltage from 0.800V to 1.550V with

25mV as shown in the previous table 1. The internal reference is trimmed to ensure output voltage precision of

±0.6% and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is pro-

grammed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is

realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code

drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an

amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are

provided (realized with a 5µA current generator up to 3.3V Typ); in this way, to program a logic "1" it is enough

to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. Programming the

"11111" code, the device enters the NOCPU mode: all mosfets are turned OFF and protections are diabled. The

condition is latched.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over

/ Under Voltage protection (OVP/UVP) thresholds.

DYNAMIC VID TRANSITION

The device is able to manage On-The-Fly VID Code changes that allow Output Voltage modification during nor-

mal device operation. The device checks every clock cycle (synchronously with the PWM ramp) for VID code

modifications. Once the new code is stable for more than one clock cycle, the reference steps up or down in

25mV increments every clock cycle until the new VID code is reached. During the transition, VID code changes

are ignored; the device re-starts monitoring VID after the transition has finished. PGOOD, signal is masked dur-

ing the transition and it is re-activated after the transition has finished while OVP / UVP are still active.

Figure 2. Dynamic VID transition

VID

Reference

VOUT

t

25mV steps transition

t

t

1 Clock Cycle Blanking Time

SOFT START AND INHIBIT

At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in

2048 clock periods as shown in figure 3.

Before soft start, the lower power MOS are turned ON after that VCCDR reaches 2V (independently by Vcc val-

ue) to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start be-

gins, the reference is increased; also the upper MOS begins to switch and the output voltage starts to increase

with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the

PGOOD signal is then driven high (See fig. 3). The Under Voltage comparator enabled when the reference volt-

age reaches 0.8V. The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-

on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies the device

shuts down. Forcing the OSC/INH/FAULT pin to a voltage lower than 0.6V (Typ.), the device enters in INHIBIT

mode: all the power mosfets are turned off and protections are disabled.

Setting the INH pin free, causes the device to restart.

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