L6910G Просмотр технического описания (PDF) - STMicroelectronics

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L6910G

ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION

STMicroelectronics 

L6910G

The response time to a load transient is different for the application or the removal of the load: if during the ap-

plication of the load the inductor is charged by a voltage equal to the difference between the input and the output

voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-

imate response time for ∆I load transient in case of enough fast compensation network response:

tapplication = -V----I-N---L--–---⋅--V-∆---O-I---U----T--

tremoval

=

--L----⋅---∆----I-

VOUT

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst

case is the response time after removal of the load with the minimum output voltage programmed and the max-

imum input voltage available.

4.7 Output Capacitor

The output capacitor is a basic component for the fast response of the power supply. In fact, during load tran-

sient, for first few microseconds they supply the current to the load. The controller recognizes immediately the

load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output

voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):

∆VOUT = ∆IOUT ⋅ ESR

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The

voltage drop due to the output capacitor discharge is given by the following equation:

∆VOUT = 2-----⋅---C-----O----U----T----⋅---(---V----I∆--N--I--MO2----UI--N--T---⋅-⋅--D-L---M-----A---X-----–-----V----O----U----T---)-

Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop

during load transient and the lower is the output voltage static ripple.

4.8 Input Capacitor

The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must

have a low ESR to minimize the losses. The rms value of this ripple is:

Irms = IOUT D ⋅ (1 – D)

Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are:

P = ESR ⋅ Ir2ms

4.9 Compensation Network Design

The control loop is a voltage mode (figure 10). The output voltage is regulated to the input Reference voltage

level (EAREF). The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide

a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. This wave is filtered by the

output filter. The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function

has a double pole at frequency FLC depending on the L-Cout resonance and a zero at FESR depending on the

output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak

oscillator voltage ∆VOSC.

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