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L4972 Просмотр технического описания (PDF) - STMicroelectronics

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L4972
ST-Microelectronics
STMicroelectronics ST-Microelectronics
L4972 Datasheet PDF : 23 Pages
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L4972A-L4972AD
CIRCUIT OPERATION
The L4972A is a 2A monolithic stepdown switching
regulatorworking in continuousmode realized inthe
new BCD Technology. This technology allows the
integration of isolatedvertical DMOS power transis-
tors plus mixed CMOS/Bipolar transistors.
The device can deliver 2A at an output voltage ad-
justable from 5.1V to 40V and contains diagnostic
and control functions that make it particularly suit-
able for microprocessor based systems.
BLOCK DIAGRAM
The block diagram shows the DMOS power tran-
sistors and the PWM control loop. Integrated func-
tions include a reference voltage trimmed to 5.1V
± 2%,soft start, undervoltagelockout, oscillator with
feedforward control, pulse by pulse current limit,
thermal shutdown and finally the reset and power
fail circuit. The reset and power fail circuit provides
an output signal for a microprocessor indicating the
status of the system.
Device turn on is around 11V with a typical 1V hys-
terysis, this threshold porvides a correct voltage for
the driving stage of the DMOS gate and the hyste-
rysis prevents instabilities.
An externalbootstrapcapacitorchargeto 12V by an
internal voltage reference is needed to provide cor-
rect gate drive to the power DMOS. The driving cir-
cuit is able to source and sink peak currents of
around 0.5A to the gate of the DMOS transistor. A
typical switching time of the current in the DMOS
transistor is 50ns. Due to the fast commutation
switching frequencies up to 200kHz are possible.
The PWM control loop consists of a sawtooth oscil-
lator, error amplifier, comparator, latch and the out-
put stage. An error signal is producedby comparing
theoutputvoltagewiththeprecise5.1V ± 2% onchip
reference. This error signal is then compared with
the sawtooth oscillator in order to generate frixed
frequency pulse width modulated drive for the out-
put stage. A PWM latch is included to eliminate
multiple pulsing within a period even in noisy envi-
ronments.
The gain and stabilityof the loop can be adjustedby
an external RC network connected to the output of
the error amplifier. A voltage feedforward control
has been added to the oscillator, this maintains su-
perior line regulation over a wide input voltage
range. Closing the loop directly gives an outputvol-
tage of 5.1V, higher voltages areobtained by insert-
ing a voltage divider.
At turn on, outputovercurrents are preventedby the
soft start function (fig. 2). The error amplifier is in-
itially clamped by an externalcapacitor,Css, and al-
lowed to rise linearly under the charge of an internal
constant current source.
Output overload protection is provided by a current
limit circuit. The load current is sensedby a internal
metalresistor connectedto a comparator.When the
load current exceeds a preset threshold, the output
of the comparator sets a flip flop which turns off the
power DMOS. The next clock pulse, from an internal
40kHz oscillator, will reset the flip flopand the power
DMOS will again conduct. This current protection
method,ensuresa constantcurrent outputwhenthe
systemis overloadedor shortcircuited and limitsthe
switching frequency, in this condition,to 40kHz. The
Reset and Power fail circuit (fig. 4), generates an
output signal when the supply voltage exceeds a
threshold programmed by an external voltage di-
vider. The reset signal, is generated with a delay
time programmedby a externalcapacitor on the de-
lay pin. When the supply voltage falls below the
threshold or the output voltage goes below 5V, the
resetoutput goes low immediately. The reset output
is an open drain.
Fig. 4A shows the case when the supply voltage is
higher than the threshold, but the output voltage is
not yet 5V.
Fig. 4B shows the case when the output is 5.1V, but
the supply voltage is not yet higher than the fixed
threshold.
The thermal protection disables circuit operation
when the junction temperature reaches about
150°C and has a hysterysis to prevent unstable
conditions.
4/23

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