SAA7165WP Просмотр технического описания (PDF) - Philips Electronics

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SAA7165WP

Video Enhancement and Digital-to-Analog processor (VEDA2)

Philips Electronics 

Philips Semiconductors

Video Enhancement and Digital-to-Analog

processor (VEDA2)

Product specification

SAA7165

PINNING

SYMBOL PIN

DESCRIPTION

REFLY

CY

SUB

UV0

1 low reference of luminance DAC (connected to VSSA1)

2 capacitor for luminance DAC (high reference)

3 substrate (connected to VSSA1)

4 UV signal input bit UV7 (digital colour-difference signal)

UV1

5 UV signal input bit UV6 (digital colour-difference signal)

UV2

6 UV signal input bit UV5 (digital colour-difference signal)

UV3

7 UV signal input bit UV4 (digital colour-difference signal)

UV4

8 UV signal input bit UV3 (digital colour-difference signal)

UV5

9 UV signal input bit UV2 (digital colour-difference signal)

UV6

10 UV signal input bit UV1 (digital colour-difference signal)

UV7

11 UV signal input bit UV0 (digital colour-difference signal)

VDDD1

VSSD1

Y0

12 +5 V digital supply voltage 1

13 digital ground 1 (0 V)

14 Y signal input bit Y7 (digital luminance signal)

Y1

15 Y signal input bit Y6 (digital luminance signal)

Y2

16 Y signal input bit Y5 (digital luminance signal)

Y3

17 Y signal input bit Y4 (digital luminance signal)

Y4

18 Y signal input bit Y3 (digital luminance signal)

Y5

19 Y signal input bit Y2 (digital luminance signal)

Y6

20 Y signal input bit Y1 (digital luminance signal)

Y7

21 Y signal input bit Y0 (digital luminance signal)

AP

22 connected to ground (action pin for testing)

SP

23 connected to ground (shift pin for testing)

MC

24 data clock CREF (e.g. 13.5 MHz); at MC = HIGH, the LLC divider-by-two is inactive

LLC

25 line-locked clock signal (LL27 = 27 MHz)

HREF

26 data clock for YUV data inputs (for active line 768Y or 640Y long)

RESET

SCL

SDA

27 reset input (active LOW)

28 I2C-bus clock line

29 I2C-bus data line

VSSD2

VDDD2

VDDA1

(R − Y)

30 digital ground 2 (0 V)

31 +5 V digital supply voltage 2

32 +5 V analog supply voltage for buffer of DAC 1

33 ±(R − Y) output signal (analog signal)

VSSA1

VSSA2

(B − Y)

34 analog ground 1 (0 V)

35 analog ground 2 (0 V)

36 ±(B − Y) output signal (analog colour-difference signal)

VDDA2

VSSA3

Y

37 +5 V analog supply voltage for buffer of DAC 2

38 analog ground 3 (0 V)

39 Y output signal (analog luminance signal)

VDDA3

40 +5 V analog supply voltage for buffer of DAC 3

1996 Aug 20

4

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