KS8001L Просмотр технического описания (PDF) - Micrel
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KS8001L Datasheet PDF : 46 Pages
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Micrel
Note 5:
MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD [3..0]
presents valid data from the MAC through the MII. TXD [3..0] has no effect when TXEN is de-asserted.
Note 6:
RMII Tx Mode: The TXD[1..0] bits are synchronous with REF_CLK. For each clock period in which TX_EN
is asserted, two bits of recovered data are recovered by the PHY.
Note 7:
SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100MBit mode,
each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times;
therefore, every ten segments represents a new byte of data. The PHY can sample any one of every 10
segments in 10MBit mode.
Strapping Options
KSZ8001
Pin Number
6, 5, 4,
3
Pin Name
PHYAD[4:1] /
RXD[0:3]
Type (Note 2)
Ipd/O
Description
PHY Address latched at power-up / reset.
The default PHY address is 00001.
25
PHYAD0 /
Ipu/O
INT#
9
PCS_LPBK / Ipd/O
Enables PCS_LPBK mode at power-up / reset.
RXDV
PD (default) = Disable, PU = Enable
10
SMII_SELECT Ipd/O
Enables SMII mode at power-up / reset.
/ RXC
PD (default) = Disable, PU = Enable
11
ISO / RXER
Ipd/O
Enables ISOLATE mode at power-up /reset.
PD (default) = Disable, PU = Enable
21
RMII_SELECT Ipd/O
Enables RMII mode at power-up / reset.
/ COL
PD (default) = Disable, PU = Enable
22
RMII_BTB/
Ipd/O
Enable RMII_BTB mode at power-up / reset.
CRS
PD (default) = Disable, PU = Enable
27
SPD100 /
Ipu/O
Latched into Register 0h bit 13 during power-up / reset.
No FEF /
PD = 10Mb/s, PU (default) = 100Mb/s.
LED1
If SPD100 is asserted during power-up / reset, this pin also
latched as the Speed Support in register 4h. (If FXEN is
pulled up, the latched value 0 means no Far _End _Fault.)
28
DUPLEX/
Ipu/O
Latched into Register 0h bit 8 during power-up / reset.
LED2
PD = Half Duplex, PU (default) = Full duplex.
If Duplex is pulled up during reset, this pin also latched as the
Duplex support in register 4h.
29
NWAYEN/
Ipu/O
Nway (auto-=Negotiation) Enable
LED3
Latched into Register 0h bit 12 during power-up / reset. PD =
Disable Auto-Negotiation, PU (default) = Enable Auto-
Negotiation
30
PD#
Ipu
Power Down Enable
PU (default) = Normal operation, PD = Power down mode
Note: Strap-in is latched during power up or reset. In some systems, the MAC RXD pins may drive high at all times causing the
PHY strap-in to be latched high during power up or system reset. In this case, it is recommended to use a strong pull down to GND
via 1kohm resistor on RXDV, RXC, and RXER pins. Otherwise, the PHY may stay in Isolate or loop back modes.
June 2009
Revision 1.04
10
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