SAA7707H Просмотр технического описания (PDF) - Philips Electronics
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SAA7707H Datasheet PDF : 48 Pages
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Philips Semiconductors
Car radio Digital Signal Processor (CDSP)
Preliminary specification
SAA7707H
7 PINNING
SYMBOL
PIN
VDACNL
1
CINT
2
FM
3
AM
4
VSSD1
5
VSSA
6
VDDD1
7
VDDA
8
RIOR
9
RVOR
10
RIOL
11
RVOL
12
Iref(int)
13
VSSO
14
VDDO
15
FIOR
16
FVOR
17
FIOL
18
FVOL
19
Vref
20
POM
21
VSSD2
22
CDCLK
23
CDWS
24
CDDAT
25
DSPRESET 26
EXDAT1
27
EXDAT2
28
VSSD9
29
TSCAN
30
A0
31
RTCB
32
SHTCB
33
VSSD7
34
EXDAT
35
EXSCL
36
EXWS
37
1997 May 30
I/O
DESCRIPTION
−
internal ground reference voltage for the level ADC
level ADC switch-mode integrator connector
I
FM level input; via this pin, the level of the received FM radio signal is fed to the
CDSP, the level information is required to enable correct functioning of the weak
signal behaviour
I
AM level input; via this pin, the level of the received AM radio signal is fed to the
CDSP
−
ground supply 1 for the DACs digital circuitry
−
ground supply for the DACs analog circuitry
−
positive supply 1 for the DACs digital circuitry
−
positive supply for the DACs analog circuitry
O analog audio current output for rear right speaker
O analog audio voltage output for rear right speaker
O analog audio current output for rear left speaker
O analog audio voltage output for rear left speaker
I
internal reference current source input for the DACs
−
ground supply for DAC output operational amplifiers
−
positive supply for DAC output operational amplifiers
O analog audio current output for front right speaker
O analog audio voltage output for front right speaker
O analog audio current output for front left speaker
O analog audio voltage output for front left speaker
I
voltage input for the internal reference buffer amplifier of the DAC
activates the Power-on mute; timing is determined with an external capacitor
−
ground supply 2 for the digital circuitry
I
clock input for CD digital audio source (I2S-bus)
I
Word Select input for CD digital audio source (I2S-bus)
I
left/right data input for CD digital audio source (I2S-bus)
I
input to reset DSP core (active LOW)
I
external input data channel 1 (front) from extra DSP chip (I2S-bus)
I
external input data channel 2 (rear) from extra DSP chip (I2S-bus)
−
ground supply 9 for the digital circuitry
scan control (active HIGH)
I2S-bus selection for slave sub-address
asynchronous reset test control block (active HIGH)
shift clock test control block (active HIGH)
−
ground supply 7 for the digital circuitry
O
output data for extra external DSP chip (I2S-bus)
O
output clock for extra external DSP chip (I2S-bus)
I/O word select input/output for extra external DSP chip (I2S-bus)
6
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