KM732V599A Просмотр технического описания (PDF) - Samsung
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KM732V599A Datasheet PDF : 15 Pages
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KM732V599A/L
PRELIMINARY
32Kx32 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS
(VDD=3.3V-5%+10%, TA=0 to 70°C)
Parameter
Symbol
Test Conditions
Min Max Unit
Input Leakage Current(except ZZ)
IIL
VDD=Max, VIN=VSS to VDD
-2
+2
µA
Output Leakage Current
IOL
Output Disabled, VOUT=VSSQ to VDDQ
-2
+2
µA
Operating Current
Device Selected, IOUT=0mA, ZZ≤VIL, All
-7
ICC
Inputs=VIL or VIH
-8
Cycle Time ≥ tCYC Min
-10
-
270
-
260
mA
-
240
-7
-
60
Device deselected, IOUT=0mA, ZZ≤VIL,
ISB
-8
-
60
mA
f=Max, All Inputs≤0.2V or ≥VDD-0.2V
-10
-
60
Standby Current
Device deselected, IOUT=0mA,
ISB1
ZZ≤0.2V, f=0,
All Inputs=fixed(VDD-0.2V or 0.2V)
-
L-Ver.
-
10
mA
1.0
mA
Device deselected, IOUT=0mA,
ISB2
ZZ ≥VDD-0.2V, f=Max,
All Inputs≤VIL or ≥VIH
-
L-Ver.
-
10
mA
500
µA
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
VOL
VOH
VIL
VIH
IOL=8.0mA
IOH=-4.0mA
-
0.4
V
2.4
-
V
-0.5* 0.8
V
2.0 5.5**
V
* VIL(Min)=-3.0V(Pulse Width≤20ns)
** In Case of I/O Pins, the Max. VIH=VDDQ + 0.5V
TEST CONDITIONS
(TA=0 to 70°C, VDD=3.3V-5%/+10%unless otherwise specified)
Parameter
Input Pulse Level
Input Rise and Fall Time(Measured at 0.3V and 2.7V)
Input and Output Timing Reference Levels
Output Load
Value
0 to 3V
2ns
1.5V
See Fig. 1
Output Load(A)
Dout
Z0=50Ω
RL=50Ω
30pF*
VL=1.5V
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
353Ω
+3.3V
319Ω
5pF*
* Capacitive Load consists of all components of
the test environment.
Fig. 1
-7-
* Including Scope and Jig Capacitance
May 1997
Rev 1.0
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