KM681001A Просмотр технического описания (PDF) - Samsung
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KM681001A Datasheet PDF : 9 Pages
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PRELIMINARY
KM681001A
CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL) : 25mA(Max.)
(CMOS) : 8mA(Max.)
Operating KM681001A - 15 : 125mA(Max.)
KM681001A - 20 : 120mA(Max.)
• Single 5.0V ±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
-No Clock or Refresh required
• Three State Outputs
• Standard Pin Configuration
KM681001AJ : 32-SOJ-400
GENERAL DESCRIPTION
The KM681001A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681001A uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681001A is packaged
in a 400mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A0
A1
A2
A3
A4
A5
A6
A7
A12
I/O1~I/O8
Data
Cont.
CLK
Gen.
CS2
CS1
WE
OE
Pre-Charge Circuit
Memory Array
512 Rows
256x8 Columns
I/O Circuit
Column Select
A8 A9 A10 A11 A13 A14 A15 A16
N.C 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
A9 11
A10 12
I/O1 13
I/O2 14
I/O3 15
Vss 16
SOJ
32 Vcc
31 A16
30 CS2
29 WE
28 A15
27 A14
26 A13
25 A12
24 OE
23 A11
22 CS1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
PIN FUNCTION
Pin Name
A0 - A16
WE
CS1, CS2
OE
I/O1 ~ I/O8
VCC
VSS
N.C
Pin Function
Address Inputs
Write Enable
Chip Selects
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
-2-
Rev 5.0
February 1998
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